caravel/verilog/gl
kareem 85f7f86c4e reharden!: gpio_control_block
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition

- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
	- to add obstruction before pdn
	- to manually insert buffers on some ports
	- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn

- misc changes:
* fix openlane makefile to properly detect interactive script

!important still need to run dynamic simulations
!important depends on some updates to openlane
2022-09-27 07:09:26 -07:00
..
__user_analog_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
__user_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
caravan.v fixed caravel netlist to use the 1803 defaults block (#94) 2022-05-03 10:36:11 -07:00
caravel.v fixed caravel netlist to use the 1803 defaults block (#94) 2022-05-03 10:36:11 -07:00
caravel_clocking.v [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
chip_io.v [DATA] Update GDS views for the chip_io/chip_io_alt/mgmt_protect_hv/mgmt_protect to match the mag view 2021-12-07 14:28:29 +02:00
chip_io_alt.v Corrected an error in verilog/gl/chip_io_alt.v, which was missing 2021-12-07 10:06:35 -05:00
digital_pll.v [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
gpio_control_block.v reharden!: gpio_control_block 2022-09-27 07:09:26 -07:00
gpio_defaults_block.v Corrected the gen_gpio_defaults.py script so that it behaves 2021-12-29 15:42:41 -05:00
gpio_defaults_block_0403.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_defaults_block_1803.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_logic_high.v harden gpio_control_block 2021-11-04 16:19:12 +02:00
housekeeping.v [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
mgmt_protect.v Mgmt protect update (#58) 2022-04-08 09:29:49 -07:00
mgmt_protect_hv.v Fix mgmt_protect_hv gate-level netlist 2021-12-07 13:38:30 +02:00
mprj2_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
mprj_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
spare_logic_block.v [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
user_id_programming.v [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
xres_buf.v [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00