caravel/verilog
M0stafaRady 37244a2514 add 3 regressions r_rtl , r_gl,r_sdf 2022-10-03 09:01:08 -07:00
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dv add 3 regressions r_rtl , r_gl,r_sdf 2022-10-03 09:01:08 -07:00
gl reharden!: gpio_control_block 2022-09-27 07:09:26 -07:00
rtl fix bug at reading from debug registers 2022-10-03 08:57:23 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00