caravel/verilog/dv/cocotb/tests
M0stafaRady 08229d6a9b Add gpio_all_bidir test but it still not working yet 2022-10-09 05:08:12 -07:00
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bitbang update input tests to cover the gpio from 32 to 37 2022-10-06 05:32:46 -07:00
common_functions increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
cpu add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
gpio Add gpio_all_bidir test but it still not working yet 2022-10-09 05:08:12 -07:00
hello_world add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
housekeeping update hk_regs_wr_wb_cpu test to include all house keeping regs 2022-10-06 11:16:07 -07:00
irq update caravel.py to disable bin 3 also 2022-10-08 01:56:41 -07:00
logicAnalyzer add test la test 2022-10-08 06:25:26 -07:00
mem add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
mgmt_gpio add new test mgmt_gpio_bidir 2022-10-03 08:56:46 -07:00
spi_master Add spi master temp created to simulate the silicon validation test and to be removed after 2022-10-04 10:46:34 -07:00
temp_partial_test add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
timer add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
uart Add test uart_loopback 2022-10-06 03:12:44 -07:00