880b499d18
Merge pull request #46 from d-m-bailey/gpio_34
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Correct gpio_defaults_block_34 instance name in caravel.mag
2022-03-22 07:53:53 -07:00
7663c2762b
Apply automatic changes to Manifest and README.rst
2022-03-22 14:29:52 +00:00
53abff5bbf
This commit fixes the issue with the user ID programming block not
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getting changed by "make ship" because the build is done in a place
where the path pointer to the user_id_programming GDS still points
back to the original caravel repository, not the user project
repository. The user_id_programming GDS was removed (no longer used),
the user_id_programming.mag file was modified to remove the path
pointer to the GDS, and the set_user_id.py script was modified to
make changes directly to the user_id_programming.mag file instead of
the GDS. An additional method was added to the set_user_id.py script
to modify the gate-level verilog/gl/user_id_programming.v to make
the user ID correct for gate-level testbench simulations.
2022-03-22 10:25:25 -04:00
cac2b1d101
Merge pull request #48 from efabless/gpio_block_mitigate_hold
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Gpio block mitigate hold
2022-03-21 12:16:24 -07:00
c4355c86fd
Apply automatic changes to Manifest and README.rst
2022-03-21 16:09:27 +00:00
be56cb19ed
Modified the GPIO control block to put additional delay on the data
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output of each GPIO block to overcome any wiring delays between
GPIO blocks that could potentially cause hold violations.
2022-03-21 12:07:12 -04:00
191139bf0e
Merge pull request #42 from efabless/RTimothyEdwards-patch-1
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Update maximum-ratings.rst
2022-03-16 16:23:55 -07:00
35781987e1
Correct gpio_defaults_block_34 instance name in caravel.mag
2022-03-14 15:04:14 -07:00
a61fc8b15d
Update maximum-ratings.rst
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Added min/max ratings for GPIO voltage and frequency
2022-03-08 08:38:11 -05:00
dab0e6a31f
Merge pull request #37 from efabless/jeffdi-patch-1
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Update Makefile
2022-02-26 09:44:51 -08:00
71372cc14e
Update Makefile
2022-02-25 17:55:26 -08:00
b17579dc6c
Merge pull request #36 from kareefardi/makefile-squashed
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makefiles and tag updates
2022-02-25 17:44:02 -08:00
f595ab9aec
bump litex tag to 5c
2022-02-25 10:50:17 -08:00
449cb47360
fix comment typo
2022-02-25 10:47:04 -08:00
0f04a43f58
- change litex tag to mpw-5c
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- warn before deleting when rerunning these targets:
install_mcw openlane pdk
- clone litex with depth=1 and single branch
- simplified pdk targets by removing these targets:
skywater-timing build-pdk skywater-library
- add clean-pdk and clean-openlane
- add make prerequisites in pdk (not sure if that's needed)
- run openlane docker non interactive
- export OPENLANE_IMAGE_NAME when running openlane docker
- add check-openlane-env target
Squashed commit of the following:
commit b7904e08ae8507bcf1ee12114e08d21a15d4646aaddf24a8b691a305f36500c249db5cba14b7a6aaf5657bbabf0fc8c4dacdc875a7b058801b3dcff403f5801b3dc28d47091c6fba67a49b0aa2
2022-02-25 10:39:11 -08:00
ff403f5d9b
Merge pull request #35 from kareefardi/pdk-non-root-install
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avoid building the pdk with docker as root user
2022-02-22 09:17:44 -08:00
ddab259ead
pass PDK_ROOT to docker
2022-02-22 07:35:11 -08:00
ffd8563e37
- set user id and groupd
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- set GIT_COMMITTER_NAME and GIT_COMMITTER_EMAIL to workaround old git
version inside magic container
2022-02-22 07:30:01 -08:00
703a986b70
Merge pull request #30 from efabless/fix_pdk_builds
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PDK Build Adjustments
2022-02-15 12:28:42 -08:00
72e8d125af
PDK Build Adjustments
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~ PDK builds now use the openlane-tools magic container instead of being native
- ability to install PDK without SRAM removed: pdk-with-sram now aliases pdk which always installs sram
2022-02-15 20:21:12 +00:00
e7ade8203d
Merge pull request #25 from efabless/ol_fix
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Change `make openlane` to `make pull-openlane` in the OpenLane Target
2022-02-03 10:15:19 -08:00
89629b357f
Change `make openlane` to `make pull-openlane` in the OpenLane Target
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Merging the image from scratch doesn't work anymore due to a dependency break.
Also, add pdk-with-sram target.
2022-02-03 18:10:53 +00:00
de724258bb
Merge pull request #22 from efabless/marwaneltoukhy-patch-1
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Update auto-update-caravel-lite.yml
2022-02-01 16:11:42 -08:00
251b113eaa
Update auto-update-caravel-lite.yml
2022-02-02 00:52:23 +02:00
e2f00e2770
Merge pull request #14 from Manarabdelaty/doc
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Documentation Updates
2022-01-18 23:13:26 -08:00
3aaad6cdf8
Merge pull request #13 from efabless/move_rectify
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Move Rectify To Caravel
2022-01-18 23:12:52 -08:00
14871f91c0
Merge pull request #9 from efabless/documentation_update
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Documentation update
2022-01-18 23:10:35 -08:00
641096e4ed
Move Rectify To Caravel
2022-01-15 23:27:38 +02:00
f6514b37f3
Update openlane.md
2022-01-14 11:27:37 -05:00
4773c5c3f8
Merge branch 'doc' of https://github.com/Manarabdelaty/caravel-1 into doc
2022-01-14 10:33:44 -05:00
c96a65d023
Update doc
2022-01-14 10:33:15 -05:00
a36d0a68fd
Update openlane.md
2022-01-14 10:25:30 -05:00
7083c96e34
Add documentation
2022-01-14 10:05:34 -05:00
d7b6b40969
Merge pull request #8 from efabless/open_pdks_264
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update open_pdks to 264
2022-01-10 07:46:30 -08:00
ae736b84d1
Merge pull request #10 from efabless/fix-gitaction-caravel-lite
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Update auto-update-caravel-lite.yml
2022-01-10 07:46:04 -08:00
86a1e55238
Merge pull request #12 from efabless/dont_compress_oas
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Update Makefile
2022-01-10 07:45:48 -08:00
ed71b5f548
Update Makefile
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exclude oas directory from compression
2022-01-09 17:26:30 -08:00
ace8cc7f4e
Update auto-update-caravel-lite.yml
2022-01-07 09:04:04 -08:00
9f2a1d5f1d
Merge pull request #7 from Manarabdelaty/update_timing_targets
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Update timing targets to run at the three corners
2022-01-06 13:48:39 -08:00
853e7ad841
Merge pull request #4 from marwaneltoukhy/main
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Converting text files in doc/other
2022-01-06 13:47:16 -08:00
25debd801c
Update Makefile
2022-01-06 11:08:42 -08:00
2f6fe69b36
Corrected the gen_gpio_defaults.py script so that it behaves
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correctly no matter how the "gpio_defaults_block.mag" and
"gl/gpio_defaults_block.v" are defined. Previously it assumed
that they both defined all bits as zero, which was not the case
for the layout. Now both define bit value 0x0402 and the script
can flip bits either direction as needed in both verilog and
layout
2021-12-29 15:42:41 -05:00
7880a52d13
Update timing targets to run at the three corners
2021-12-29 19:11:13 +02:00
7a45a096a5
Added a testbench that exercises the SRAM 2nd (read-only) port, as
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it was configured for the caravel_pico SoC, with the housekeeping
SPI able to access the upper 256-word section of the memory if the
CSB bit in the housekeeping control register is cleared. This
testbench tests both access through housekeeping and access directly
from the SoC through the memory-mapped address.
2021-12-29 11:24:17 -05:00
b6e15baec9
added rst dir and converted all docs/other/*.txt to .rst
2021-12-27 19:17:32 +02:00
6648513a0e
Update clamp_list.rst
2021-12-27 19:09:18 +02:00
ccce8a0f21
Create power_control.rst
2021-12-27 17:29:46 +02:00
9470db9021
Create management_protect.rst
2021-12-27 17:23:17 +02:00
45c2c643f5
Merge branch 'efabless:main' into main
2021-12-27 17:11:10 +02:00
0b17ee1d77
Create gpio.rst
2021-12-27 17:10:59 +02:00
Jeff DiCorpo
RTimothyEdwards
Tim Edwards
D. Mitch Bailey
kareem
Donn
Marwan Abbas
Manar
Marwan Abbas