Merge pull request #48 from efabless/gpio_block_mitigate_hold

Gpio block mitigate hold

manifest

@@ -13,7 +13,7 @@ d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76  verilog/rtl/chip_io.v
 126aff02aa229dc346301c552d785dec76a4d68e  verilog/rtl/clock_div.v
 36af0303a0e84ce4a40a854ef1481f8a56bc9989  verilog/rtl/digital_pll.v
 ce49f9af199b5f16d2c39c417d58e5890bc7bab2  verilog/rtl/digital_pll_controller.v
-dca26d9169bf4090ac2025a8b981408f5bae4ef4  verilog/rtl/gpio_control_block.v
+3a62ce6627741ec3eaf798a23807ef15c46475a4  verilog/rtl/gpio_control_block.v
 9c92ddf1391fa75ee906e452e168ca2cdd23bd18  verilog/rtl/gpio_defaults_block.v
 32d395d5936632f3c92a0de4867d6dd7cd4af1bb  verilog/rtl/gpio_logic_high.v
 5469b880904d6dd5d1eba6f026b3582810df412c  verilog/rtl/housekeeping.v

verilog/rtl/gpio_control_block.v

@@ -142,6 +142,8 @@ module gpio_control_block #(
     wire gpio_in_unbuf;
     wire gpio_logic1;
     wire serial_data_pre;
+    wire serial_data_post_1;
+    wire serial_data_post_2;
 
     /* Serial shift for the above (latched) values */
     reg [PAD_CTRL_BITS-1:0] shift_register;
@@ -155,8 +157,34 @@ module gpio_control_block #(
     assign resetn_out = resetn;
     assign serial_load_out = serial_load;
 
-    /* Serial data should be buffered again to avoid hold violations */
-    assign serial_data_out = serial_data_pre & one;
+    /* Serial data should be buffered again to avoid hold violations	*/
+    /* Do this in two ways:  (1) Add internal delay cells, and (2)	*/
+    /* add a final logic gate after that.  The logic gate is		*/
+    /* synthesized and will be sized appropriately for an output buffer	*/
+
+    sky130_fd_sc_hd__dlygate4sd2 data_delay_1 (
+`ifdef USE_POWER_PINS
+            .VPWR(vccd),
+            .VGND(vssd),
+            .VPB(vccd),
+            .VNB(vssd),
+`endif
+            .X(serial_data_post_1),
+            .A(serial_data_pre),
+    );
+
+    sky130_fd_sc_hd__dlygate4sd2 data_delay_2 (
+`ifdef USE_POWER_PINS
+            .VPWR(vccd),
+            .VGND(vssd),
+            .VPB(vccd),
+            .VNB(vssd),
+`endif
+            .X(serial_data_post_2),
+            .A(serial_data_post_1),
+    );
+
+    assign serial_data_out = serial_data_post_2 & one;
 
     always @(posedge serial_clock or negedge resetn) begin
 	if (resetn == 1'b0) begin