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caravel
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669 Commits

Author SHA1 Message Date
Tim Edwards d0f74db23b Updated pinout in documentation (doc/README file) 2021-10-20 10:24:41 -04:00
Tim Edwards 000a5266ef Corrected an error in the bitbang testbench (but it does not cause the 
testbench to pass).
 2021-10-19 23:10:51 -04:00
Tim Edwards 184f4a637c Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and 
storage.  Not all of these pass simulation checks.  Added back the
bit-bang control of the GPIO programming.  Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports.  There is not yet a testbench for the SRAM read-only
interface.
 2021-10-19 19:05:47 -04:00
Tim Edwards 767342e183 Added a completely revised sysctrl testbench based on accessing the 
housekeeping SPI through the back-door wishbone interface.  Checks
most of the SPI registers (but could do more).
 2021-10-19 17:32:20 -04:00
Tim Edwards e2f6a02688 Added and verified testbenches timer, timer2, uart, and user_pass_thru. 2021-10-18 21:53:09 -04:00
Tim Edwards 0fa2e3bb89 Added testbenches for irq, mem, mprj_ctrl, and pass_thru (note that "mem" 
does not pass yet and still needs to be debugged).
 2021-10-18 20:32:50 -04:00
Tim Edwards 2e57b5da08 Added and debugged two more testbenches, gpio_mgmt and hkspi. 2021-10-18 11:25:26 -04:00
Tim Edwards 33ca4e11ef Additional corrections, mostly to the housekeeping module. The 
top-level simulation now passes the GPIO testbench.
 2021-10-17 21:38:40 -04:00
Tim Edwards 1863a7c529 A number of small corrections. 2021-10-16 23:55:57 -04:00
Tim Edwards 842200b7ec Changed the memory map to move the 2e and 2f wishbone domains into 
the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262...  Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
 2021-10-16 17:58:36 -04:00
Tim Edwards 2f74fa83ee Reinstated the logic analyzer as a standard interface for the 
management SoC.
 2021-10-16 17:42:24 -04:00
Tim Edwards bdfa747145 First major update; current code passes syntax checks in iverilog 
and simulates, but fails testbench (not surprising at this stage).
 2021-10-15 21:49:49 -04:00
Tim Edwards f1909cab52 Merge branch 'main' of github.com:efabless/caravel-openframe into main 
Pulling recent commits.
 2021-10-12 16:32:48 -04:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged 
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
 2021-10-12 16:31:42 -04:00
Jeff DiCorpo fd885a9b10
Update README.md 2021-10-12 10:28:29 -07:00
Jeff DiCorpo fac8558a37
Update README.md 2021-10-12 09:38:05 -07:00
Jeff DiCorpo 271f978bc8
Update README.md 2021-10-08 08:00:07 -07:00
Jeff DiCorpo 9615b3d0fc
Update README.md 2021-10-07 11:34:30 -07:00
Jeff DiCorpo 1a7a9dcc16
Initial commit 2021-10-07 11:32:23 -07:00