11 Commits

Author	SHA1	Message	Date
mo-hosni	d71787a51a	add `ANTGATERATIO` in all the lefs through `scripts/insert_ant_areas.py`	2023-05-22 05:41:12 -07:00
kareem	68063ddadc	reharden: digital_pll ... ~ increase width for more spread decaps + add or cells to cell exclude ~ change placement density in accordance to area ~ change padding to allow for space for decaps	2022-10-18 07:07:32 -07:00
kareem	712b784e16	reharden!: digital_pll ... ~ disable or gate + add nosynth list file	2022-10-17 12:33:25 -07:00
kareem	e5d9788a43	reharden!: digital_pll ... ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched	2022-10-17 10:56:01 -07:00
kareem	59743f4832	change buf16 to clkbuf16 and reimplement	2022-10-13 06:54:55 -07:00
kareem	0eed96f33f	reharden: digital_pll ... ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables	2022-10-13 06:21:08 -07:00
manarabdelaty	966b1f22bb	[DATA] Update digital_pll	2021-12-07 13:19:02 +02:00
manarabdelaty	0067bd5b7c	[DATA] Update caravel_clocking/digital_pll/housekeeping	2021-12-02 21:09:43 +02:00
manarabdelaty	37a07e291b	[DATA] Update digital_pll pin placement to have it align with the HK	2021-11-19 01:28:40 +02:00
manarabdelaty	72b2c724c9	[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz	2021-11-15 15:50:43 +02:00
manarabdelaty	bee7b4ed78	Add initial config for the digital_pll	2021-11-08 13:34:59 +02:00