e067e558a3
update `digital_pll` and `caravel_clocking` sdc pll clocks constraints ( #293 )
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* update pll clocks period constraint to `11.76ns (85MHz)` instead of `6.6667ns (150 MHz)`
* update sdcs Rev and date
2022-10-21 07:45:56 -07:00
19ce4a5906
add signoff results for `digital_pll`:
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- signoff summary report
- DRC and LVS reports
- STA timing reports for all corners
- generated lib files for all corners
- generated sdf files for all corners
2022-10-19 07:05:38 -07:00
68063ddadc
reharden: digital_pll
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~ increase width for more spread decaps
+ add or cells to cell exclude
~ change placement density in accordance to area
~ change padding to allow for space for decaps
2022-10-18 07:07:32 -07:00
712b784e16
reharden!: digital_pll
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~ disable or gate
+ add nosynth list file
2022-10-17 12:33:25 -07:00
e5d9788a43
reharden!: digital_pll
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~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys
!need to verify that the oscillator remains untouched
2022-10-17 10:56:01 -07:00
df2cd63152
Re-implemented Macros generated libs ( #251 )
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* move `gpio_control_block` libs to `./signoff/<design_name>/standalone_pvr/primetime-signoff/lib/`
* add generated libs for `housekeeping`
* add generated lib for `caravel_clocking`
* add generated libs for `digital_pll`
* add generated libs for `mgmt_protect`
2022-10-15 18:30:46 -07:00
9e1b6610d1
Merge pull request #234 from efabless/openlane-runs-config
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+ add caravel_clocking & digital_pl & gpio_control_block openlane runs config.tcl file
2022-10-14 23:47:44 +02:00
ea6badcd67
+ add caravel_clocking & digital_pl & gpio_control_block openlane run config.tcl file
2022-10-14 14:28:47 -07:00
f69a522f19
update script to get the signoff sdc from directory `./signoff/<design name>/<design name>.sdc`
2022-10-14 13:57:16 -07:00
c83d7b6a52
changed paths of openlane signoff spef and sdfs
2022-10-13 09:11:54 -07:00
59743f4832
change buf16 to clkbuf16 and reimplement
2022-10-13 06:54:55 -07:00
0eed96f33f
reharden: digital_pll
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~ reimplement digital_pll using updated RTL
~ changes in config to generate same PDN
~ change deprecated variables
2022-10-13 06:21:08 -07:00
78cec109cc
add signoff sdc dir
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move sdc generated from openlane to signoff/<design name>/openlane-signoff
rearrange spef directory with RC corners spefs
2022-10-12 07:28:32 -07:00
966b1f22bb
[DATA] Update digital_pll
2021-12-07 13:19:02 +02:00
0067bd5b7c
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 21:09:43 +02:00
37a07e291b
[DATA] Update digital_pll pin placement to have it align with the HK
2021-11-19 01:28:40 +02:00
72b2c724c9
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 15:50:43 +02:00
bee7b4ed78
Add initial config for the digital_pll
2021-11-08 13:34:59 +02:00
passant5
Passant
kareem
marwaneltoukhy
manarabdelaty