2b156997cb
Added a new module with "spare logic" for metal mask fixes.
2021-11-24 09:23:22 -05:00
bb1c9fe528
Removed two references for single-macro verilog files that are no
...
longer in the PDK but have been folded into larger library files.
With the most recent push to open_pdks to fix an error in the I/O
verilog library, the verilog testbenches once again pass.
2021-11-15 17:53:48 -05:00
856539ca59
Update storage testbench to work with one 2K block
2021-11-12 17:14:21 +02:00
1d359690ac
Added testbench for checking that the housekeeping SPI is accessible when
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the user area is powered down. Because this requires some changes to the
padframe definition, this testbench currently fails.
2021-11-02 21:58:47 -04:00
dd66d1e5ca
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 21:43:09 -04:00
bc9944ce20
Updated the caravan netlist and implemented the caravan testbench.
2021-10-25 15:08:13 -04:00
e5c90daddd
Implemented a system for setting the GPIO power-on defaults through
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via programming. The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file. For the verilog, they are
applied as parameters. For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
2021-10-23 17:18:30 -04:00
bdfa747145
First major update; current code passes syntax checks in iverilog
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and simulates, but fails testbench (not surprising at this stage).
2021-10-15 21:49:49 -04:00
332f9ec2e7
Seeding with documentation of pinout and verilog RTL (mostly unchanged
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from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
2021-10-12 16:31:42 -04:00
Tim Edwards
manarabdelaty