riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fix a typo in caravel_core RTL

This commit is contained in:
mo-hosni 2024-03-17 12:09:49 +02:00
parent 0dbdb4df96
commit efc0304e1e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
verilog/rtl/caravel_core.v
View File

@ -1429,7 +1429,7 @@ module caravel_core (
); );
/* Section 2 GPIOs (GPIO 32 to 34) */ /* Section 2 GPIOs (GPIO 32 to 34) */
gpio_control_block_mgmt gpio_control_in_2_3 [2:0] ( gpio_control_block gpio_control_in_2_3 [2:0] (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.vccd(vccd), .vccd(vccd),
.vssd(vssd), .vssd(vssd),