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SOFA/FPGA1212_QLSOFA_HD_PNR
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tangxifan 5183326946
Update generate_testbench.openfpga 
Address #124
 		2021-07-24 14:59:34 -07:00
..
FPGA1212_QLSOFA_HD_Verilog [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
FPGA1212_QLSOFA_HD_task Update generate_testbench.openfpga 2021-07-24 14:59:34 -07:00
Verification [QLSOFA_HD] Updated QLSOFA_HD Verification results 2020-12-14 13:38:08 -07:00
fpga_top [DRCFix] Fixed filler cell boundary 2021-02-10 22:43:08 -07:00
modules [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
Makefile Minor changes before demo 2021-05-14 11:30:22 -06:00
README.md Updated all the results 2020-12-20 03:44:00 -07:00
config.sh [Flow] Adding Makefile for running task 2021-04-03 17:54:59 -06:00

README.md

FPGA1212_FLAT_HD_SKY_PNR

12x12 FPGA designed using hierarchical flow and SKY130_FD_SC_HD. Flat Module design style