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Minor changes before demo

This commit is contained in:
Ganesh Gore 2021-05-14 11:30:22 -06:00
parent fd56949ead
commit 698a833475
2 changed files with 2 additions and 0 deletions
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FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga
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@ -46,6 +46,7 @@ build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.xml --format xml
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists

1
FPGA1212_QLSOFA_HD_PNR/Makefile
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@ -10,6 +10,7 @@ OPTIONS =
.SILENT:
.ONESHELL:
.PHONY: runOpenFPGA
runOpenFPGA:
SECONDS=0
source config.sh