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212 Commits 16 Branches 1 Tag 1.8 GiB
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212 Commits

Author SHA1 Message Date
tangxifan b08b77994c [HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA 2020-11-20 18:13:37 -07:00
tangxifan 06c732325b [Testbench] Add post-PnR testbench for benchmark simon_serial 2020-11-20 17:05:42 -07:00
tangxifan 5edb154140 [Testbench] Add post PnR testbench for benchmark bin2bcd 2020-11-20 16:59:38 -07:00
tangxifan b60e0aa2cd [Testbench] Add post-PnR testbench for benchmark routing_test 2020-11-20 16:47:03 -07:00
tangxifan aa79cc3577 [Testbench] Add post-PnR testbench for benchmark counter 2020-11-20 16:34:32 -07:00
tangxifan a5a92d719a [Script] Remove benchmarks which cannot fit from task-run 2020-11-20 15:44:30 -07:00
tangxifan ce188bbe2c [Script] Add benchmarks to openfpga testbench generator task-run 2020-11-20 15:35:57 -07:00
tangxifan 326c297cb1 [Benchmark] Add more opencore benchmarks for testing 2020-11-20 15:31:58 -07:00
tangxifan b07a156432 [Script] Deploy more testing benchmarks to the OpenFPGA testbench generation task 2020-11-20 15:10:29 -07:00
tangxifan bd17e6b2af [Benchmark] Add more basic benchmarks for post-PnR testing 2020-11-20 15:06:44 -07:00
tangxifan 7145f7ccd4 [Doc] Add documentation about the testbenches 2020-11-20 13:59:15 -07:00
tangxifan 3756c25572 [Testbench] Enhance checking codes. Now 'X' or 'Z' signal will fail in self-checking 2020-11-20 13:51:26 -07:00
tangxifan 5a2f1e7607 [TESTBENCH] Place the include lines for post-PnR skywater cell netlists in a separated netlist, so that it can be shared among post-PnRed testbenches 2020-11-20 13:33:13 -07:00
tangxifan 40eccfa0ba [Testbench] Update post-PnR testbenches for configuration chain and scan-chain and enhance checking codes 2020-11-20 11:45:51 -07:00
tangxifan ae82946052 [Testbench] Update and2_latch post-pnr testbench 2020-11-20 11:15:01 -07:00
tangxifan e58fc97794 [Testbench] Update post-pnr test for latest PnRed netlist 2020-11-20 10:55:59 -07:00
tangxifan 6fa5e935fa [HDL] Update wrapper generator to use tri-state buffer for outputs 2020-11-19 17:14:50 -07:00
tangxifan dde0656968 [HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes 2020-11-19 16:31:06 -07:00
tangxifan ca716234f1 Merge branch 'master' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev 2020-11-19 16:14:39 -07:00
tangxifan 95107f9c7a [Doc] Correct bug in I/O circuit design and use svg instead of png in documentation 2020-11-19 16:13:27 -07:00
tangxifan 8036d4f39d
Merge pull request #29 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-11-19 14:44:09 -07:00
Ganesh Gore 37e72cffb5 [HDL] Updated wrapper generation script 2020-11-18 23:15:26 -07:00
Ganesh Gore 8818449c36 Merge remote-tracking branch 'origin/xt_dev' into ganesh_dev 2020-11-18 21:21:03 -07:00
Laboratory for Nano Integrated Systems (LNIS) f927916946
Merge pull request #28 from LNIS-Projects/xt_dev 
Update I/O arrangement to avoid congestion in backend
 2020-11-18 20:52:24 -07:00
tangxifan 014a6b56ce [HDL] Add clock switch to wrapper 2020-11-18 20:50:10 -07:00
tangxifan 33824bf179 [HDL] Update caravel wrapper for new I/O assignment 2020-11-18 20:44:54 -07:00
tangxifan ca458b22f0 [Doc] Bug fix in io assignment 2020-11-18 20:31:30 -07:00
tangxifan 39b2b99ac2 [Doc] Update I/O switch by considering clock switches 2020-11-18 19:47:24 -07:00
tangxifan 655e19de6a [Doc] Update I/O arrangement to avoid congestion in backend 2020-11-18 19:11:35 -07:00
Ganesh Gore 3daabd5448 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-11-18 17:55:52 -07:00
Laboratory for Nano Integrated Systems (LNIS) 720c65bc7f
Merge pull request #27 from LNIS-Projects/xt_dev 
Fabric Testbenches
 2020-11-18 16:28:24 -07:00
tangxifan f5d18d33ea [Testbench] Add scan-chain testbench for post-pnr verification 2020-11-18 16:23:37 -07:00
tangxifan 2c590e6fb2 [Doc] Fix a typo in the resource count 2020-11-18 16:21:17 -07:00
tangxifan 439c73d211 [Testbench] Add configuration chain test benches for pre- and post- pnr simulation 2020-11-18 15:58:00 -07:00
tangxifan ce91890a0e [HDL] Now use a proper drive strength of 4 in the digital I/O cells 2020-11-18 11:58:21 -07:00
tangxifan 3ae41e2207 [Arch] Double checked I/O default direction set up in OpenFPGA architecture. Add comments for this point 2020-11-18 11:56:22 -07:00
tangxifan ea5c616339 [Doc] Enhance I/O management guidelines 2020-11-18 11:53:37 -07:00
tangxifan da0469728b [Doc] Add guidelines for setting unuses I/Os 2020-11-18 11:50:21 -07:00
Laboratory for Nano Integrated Systems (LNIS) 4badd4dbae
Merge pull request #26 from LNIS-Projects/xt_dev 
Update I/O arrangement for Caravel Project Wrapper
 2020-11-18 11:35:43 -07:00
tangxifan 4837e6d424 [HDL] Remove out-of-data wrapper 2020-11-18 11:30:53 -07:00
tangxifan a916ce7e03 [HDL] Bug fix in the caravel fpga wrapper built with hd cell library 2020-11-18 11:29:37 -07:00
tangxifan d36cb8abe7 [HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script 2020-11-17 21:44:13 -07:00
tangxifan ed98aa27a8 [Doc] Add I/O cell truth table 2020-11-17 21:12:08 -07:00
tangxifan 2b0c5c67e9 [Doc] Update I/O arrangement to be consistent with new arch 2020-11-17 20:45:20 -07:00
Laboratory for Nano Integrated Systems (LNIS) 2fe312258e
Merge pull request #25 from LNIS-Projects/xt_dev 
Create digital I/O Cell with protection circuitry
 2020-11-17 20:11:56 -07:00
tangxifan 58440b8c42 [HDL] Bug fix in I/O cell 2020-11-17 20:03:20 -07:00
tangxifan 1bfc793600 [Arch] Bug fix due to the use of embedded I/O cell 2020-11-17 19:55:04 -07:00
tangxifan 6a27eca809 [Arch] Update arch to use digital I/O circuitry 2020-11-17 19:34:58 -07:00
tangxifan 8803b30b26 [HDL] Rename por of I/O cell to be consistent with documentation 2020-11-17 19:33:53 -07:00
tangxifan b1ce66e8ce [Doc] Update I/O circuitry details 2020-11-17 19:31:04 -07:00