[Benchmark] Add more basic benchmarks for post-PnR testing

BENCHMARK/bin2bcd/bin2bcd.v

@@ -0,0 +1,38 @@
+//-------------------------------------------------------------------
+// Function: Binary to Decimal converter
+// Source: 
+//   https://verilogcodes.blogspot.com/2015/10/verilog-code-for-8-bit-binary-to-bcd.html
+//-------------------------------------------------------------------
+module bin2bcd(
+     bin,
+     bcd
+    );
+
+    
+    //input ports and their sizes
+    input [7:0] bin;
+    //output ports and, their size
+    output [11:0] bcd;
+    //Internal variables
+    reg [11 : 0] bcd; 
+    reg [3:0] i;   
+     
+     //Always block - implement the Double Dabble algorithm
+     always @(bin)
+        begin
+            bcd = 0; //initialize bcd to zero.
+            for (i = 0; i < 8; i = i+1) //run for 8 iterations
+            begin
+                bcd = {bcd[10:0],bin[7-i]}; //concatenation
+                    
+                //if a hex digit of 'bcd' is more than 4, add 3 to it.  
+                if(i < 7 && bcd[3:0] > 4) 
+                    bcd[3:0] = bcd[3:0] + 3;
+                if(i < 7 && bcd[7:4] > 4)
+                    bcd[7:4] = bcd[7:4] + 3;
+                if(i < 7 && bcd[11:8] > 4)
+                    bcd[11:8] = bcd[11:8] + 3;  
+            end
+        end     
+                
+endmodule

BENCHMARK/bin2bcd/bin2bcd_tb.v

@@ -0,0 +1,31 @@
+//-------------------------------------------------------------------
+// Function: Testbench for the Binary to Decimal converter
+// Source: 
+//   https://verilogcodes.blogspot.com/2015/10/verilog-code-for-8-bit-binary-to-bcd.html
+module tb_bin2bcd;
+
+    // Input
+    reg [7:0] bin;
+    // Output
+    wire [11:0] bcd;
+    // Extra variables
+    reg [8:0] i;
+
+    // Instantiate the Unit Under Test (UUT)
+    bin2bcd uut (
+        .bin(bin), 
+        .bcd(bcd)
+    );
+
+//Simulation - Apply inputs
+    initial begin
+    //A for loop for checking all the input combinations.
+        for(i=0;i<256;i=i+1)
+        begin
+            bin = i; 
+            #10; //wait for 10 ns.
+        end 
+        $finish; //system function for stoping the simulation.
+    end
+      
+endmodule

BENCHMARK/counter/counter.v

@@ -1,16 +1,16 @@
-module counter(clk_counter, q_counter, rst_counter);
+module counter(clk, q, rst);
 
-    input clk_counter;
-    input rst_counter;
-    output [7:0] q_counter;
-    reg [7:0] q_counter;
+    input clk;
+    input rst;
+    output [7:0] q;
+    reg [7:0] q;
 
-    always @ (posedge clk_counter)
+    always @ (posedge clk)
     begin
-        if(rst_counter)
-		q_counter <= 8'b00000000;
+        if(rst)
+			q <= 8'b00000000;
 	else
-		q_counter <= q_counter + 1;
+		q <= q + 1;
     end
 
 endmodule

BENCHMARK/counter/counter_tb.v

@@ -21,4 +21,4 @@ module counter_tb;
 		#5000 $stop;
 	end
 
-endmodule
+endmodule

BENCHMARK/routing_test/routing_test.act

@@ -0,0 +1,10 @@
+IN0 0.505000 0.204400
+IN1 0.491000 0.206000
+IN2 0.472000 0.204400
+clk 0.500000 2.000000
+OUT1 0.491000 0.206000
+OUT0 0.505000 0.204400
+OUT2 0.472000 0.204400
+n15 0.491000 0.101146
+n18 0.505000 0.103222
+n21 0.472000 0.096477

BENCHMARK/routing_test/routing_test.blif

@@ -0,0 +1,16 @@
+# Benchmark "routing_test" written by ABC on Tue Apr 21 18:25:21 2020 
+.model routing_test 
+.inputs IN0 IN1 IN2 clk  
+.outputs OUT0 OUT1 OUT2  
+ 
+.latch n15 OUT1 re clk 2 
+.latch n18 OUT0 re clk 2 
+.latch n21 OUT2 re clk 2 
+ 
+.names IN1 n15 
+1 1 
+.names IN0 n18 
+1 1 
+.names IN2 n21 
+1 1 
+.end 

BENCHMARK/routing_test/routing_test.v

@@ -0,0 +1,19 @@
+
+module routing_test(IN0,IN1,IN2, clk, OUT0,OUT1,OUT2);
+
+input wire IN0,IN1,IN2,clk;
+
+output reg OUT0, OUT1, OUT2;
+
+always @(posedge clk)
+	begin
+
+		OUT0  <=  IN0;
+		OUT1  <=  IN1;
+		OUT2  <=  IN2;
+
+	end
+
+
+
+endmodule