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782 Commits

Author SHA1 Message Date
Ganesh Gore 31a73a42ba Updated design with new architecure and merged grid_io 2020-11-06 22:35:31 -07:00
tangxifan a36cc83280
Merge pull request #11 from LNIS-Projects/xt_dev 
[Arch] Use single-output DFF to further compress area
 2020-11-06 15:15:52 -07:00
tangxifan 8d84d83eab [Arch] Use single-output DFF to further compress area 2020-11-06 11:47:31 -07:00
Laboratory for Nano Integrated Systems (LNIS) d9cbaa3eec
Merge pull request #10 from LNIS-Projects/xt_dev 
Patch to have UNIQUE routing blocks
 2020-11-05 22:23:50 -07:00
tangxifan 6811604e5c [Arch] Revert back to a lower Fc for area efficiency 2020-11-05 22:23:11 -07:00
tangxifan fe3bf8ba58 [Arch] Patch to have UNIQUE routing blocks 2020-11-05 22:20:51 -07:00
Laboratory for Nano Integrated Systems (LNIS) 2ed8bee461
Merge pull request #9 from LNIS-Projects/xt_dev 
Minor patch on arch for Caravel to force unique CBY
 2020-11-05 21:58:08 -07:00
tangxifan 1892dd5205 [Arch] Minor patch on arch to force unique CBY 2020-11-05 21:55:43 -07:00
Laboratory for Nano Integrated Systems (LNIS) e6c51dbb42
Merge pull request #8 from LNIS-Projects/xt_dev 
Addition of Architectures Tuned for Caravel SoC Interface
 2020-11-05 15:19:39 -07:00
tangxifan e952eb951d [HDL] Add preprocessing flags for running functional verification 2020-11-05 11:29:23 -07:00
tangxifan 6b474ce422 [Arch] Patch openfpga arch for new syntax on I/O 2020-11-05 10:37:37 -07:00
tangxifan bbdd13ac16 [Script] Add openfpga task run for caravel architecture 2020-11-05 10:25:23 -07:00
tangxifan a25b8252f3 [Arch] Add openfpga arch template for the caravel 2020-11-05 10:20:54 -07:00
tangxifan 64d1113461 [HDL] Add HDL codes for the FPGA I/O cell tuned for Caravel 2020-11-05 10:18:52 -07:00
tangxifan 5b69b0a087 [Arch] Add the VPR architecture tuned for Caravel I/O interface 2020-11-05 09:43:38 -07:00
Ganesh Gore 89d42cc03d Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-11-03 13:15:24 -07:00
Laboratory for Nano Integrated Systems (LNIS) 04615e0709
Merge pull request #7 from LNIS-Projects/xt_dev 
Add Architecture with pure digital I/O for Embedded FPGA Fabric
 2020-11-03 10:10:29 -07:00
tangxifan 1264054cab [Arch] Bug fix in netlist path 2020-11-03 09:57:25 -07:00
tangxifan 48d8f8b664 [Arch] Same patch on the scff on another arch 2020-11-03 09:54:30 -07:00
tangxifan 533a6ab90f [Arch] Use an exact fit scan-chain flip-flop in the architectures 2020-11-03 09:53:16 -07:00
tangxifan a46d1bd492 [Doc] Add README to SDC and Testbench directories 2020-11-03 09:27:06 -07:00
tangxifan 8702073354 [Doc] Add readme for HDL directory 2020-11-03 09:23:33 -07:00
tangxifan 12881d7a31 [HDL] Move verilog wrapper to HDL directory 2020-11-03 09:19:43 -07:00
tangxifan b5c781f555 [Arch] Patch the HDL netlist name to differetiate between cell types 2020-11-03 09:17:22 -07:00
tangxifan 40ca8dfbe3 [Arch] Update architecture files to use the wrapper files 2020-11-03 09:14:47 -07:00
tangxifan b67896a225 [HDL] Add embedded I/O HDL wrapper using the high density cells 2020-11-03 09:05:20 -07:00
tangxifan 0958d9c50f [Script] Add openfpga task run for embedded architecture 2020-11-02 20:09:35 -07:00
tangxifan c26f8a5aac [Arch] Add architecture files for embedded FPGA IP 2020-11-02 19:55:40 -07:00
Laboratory for Nano Integrated Systems (LNIS) 42589c96b7
Merge pull request #6 from LNIS-Projects/xt_dev 
Bug fix in the k4 architecture that blocks verification
 2020-11-02 18:49:15 -07:00
tangxifan 3f10b49eeb [PDK] Add standard cell wrapper 2020-11-02 11:28:29 -07:00
tangxifan bff4fdfdc1 [Arch] Update pin equivalence for the non-LR non-adder k4 arch 2020-11-02 11:27:44 -07:00
tangxifan 23ac6af11f [Arch] Bug fix on the wrong verilog netlist path 2020-11-01 15:45:41 -07:00
tangxifan a03f0908e2
Merge pull request #5 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-10-31 12:05:59 -06:00
Ganesh Gore ec9a02f9e0 Added 12x12 FPGA design with SKY130_SC_HD cells 2020-10-28 12:41:37 -06:00
Ganesh Gore 934abfac9b Added SPEF files in git lfs 2020-10-28 12:39:15 -06:00
Ganesh Gore 6dd9905541 [UPDATE] Updated reports and screenshots 2020-10-27 15:51:16 -06:00
Ganesh Gore 72ff141046 [DESIGN] Updated FPGA22 Design 
+ Utilization increased to 60%
+ Added track offset
+ Added Power ring
+ Added Tapcells
+ Added additional reports and screenshot to track improvements
 2020-10-27 14:54:19 -06:00
tangxifan 2d5a1cdecd
Merge pull request #4 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-10-27 13:58:12 -06:00
Ganesh Gore 030679a518 dropped symbolic link 2020-10-27 11:21:20 -06:00
Ganesh Gore 8b22960ddc [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
Ganesh Gore 51a89fedff Initialize GitLFS 2020-10-26 23:37:24 -06:00
Laboratory for Nano Integrated Systems (LNIS) 4d0f76f127
Merge pull request #3 from LNIS-Projects/xt_dev 
Architecture update on a k4 arch without hard adder
 2020-10-24 12:01:52 -06:00
tangxifan af4b89b37c [Arch] Bug fix in non-adder k4 arch 2020-10-24 12:00:20 -06:00
tangxifan 7125a1ed5b [Script] Add task cleanup to setup script 2020-10-24 12:00:03 -06:00
tangxifan 163108c2c5 [Script] Add openfpga task for non-adder k4 arch 2020-10-24 11:49:41 -06:00
tangxifan eaf5ba6074 [Arch] Add openfpga arch for non-adder k4 vpr arch 2020-10-24 11:44:41 -06:00
tangxifan bd834d4086 [Arch] Add a simplified k4 architecture without hard adders 2020-10-24 11:37:04 -06:00
tangxifan 935ea038c0 [Script] Minor format fix 2020-10-15 10:00:50 -06:00
tangxifan 298f259064 [Script] Add openfpga task run to setup script 2020-10-15 09:49:46 -06:00
tangxifan 7193eeef88
Merge pull request #2 from LNIS-Projects/xt_dev 
Xt dev
 2020-10-14 22:15:36 -06:00