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705 Commits 16 Branches 1 Tag 1.8 GiB
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61 Commits

Author SHA1 Message Date
Maciej Kurc 0823e7e878 Corrected destination pb_type offsets for IO registers in k4_N8 OpenFPGA arch XML. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-08 10:41:48 +01:00
Kevin Liao b5be7692c4 (1)CFG_DONE to add is_config_enable(2)reset default=1 under tile_annotations 2021-01-29 08:56:59 -08:00
Kevin Liao 924b3d51de correct dummy stdcell verilog pointer 2021-01-26 15:45:59 -08:00
Kevin Liao 84c217bc56 replace CFGSDFFR with QL_CCFF and fix testbench related 2021-01-26 09:41:23 -08:00
Kevin Liao f7af0b40cf rename prefix for circuit_model iopad 2021-01-21 20:50:00 -08:00
Tarachand Pagarani 9c1b2ca4d4 update the name of IO cell and ports to be consistent with QL names 2021-01-21 04:18:25 -08:00
Tarachand Pagarani 36739d9c7c Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface 2021-01-17 23:55:54 -08:00
Tarachand Pagarani 72d8d20356 1. Add 4 clocks to IO interfaces 
2. Mux the clock with the output for sending the clock out of the FPGA
 2021-01-17 23:54:39 -08:00
Kevin Liao 69ed6b5e27 forgot to add new port, IO_ISOL_N, for EMBEDDED_IO_HD 2021-01-15 12:48:32 -08:00
Kevin Liao f428234df8 correct EMBEDDED_IO_HD verilog pointer 2021-01-15 11:08:43 -08:00
Tarachand Pagarani ac355c370d merge latest changes from master 2021-01-15 00:26:25 -08:00
Kevin Liao 806303af11 remove soft_adder, and fix Test_en from ccff 2021-01-14 20:14:04 -08:00
Tarachand Pagarani 3f5409eee2 add 4 global clocks 2021-01-14 02:28:07 -08:00
Lalit Sharma ba34ebb4e5 Removing commented sections/attributes. Also corrected indentation 2021-01-13 00:48:03 -08:00
Lalit Sharma 6702de4516 Merging latest changes from master related to tile_port deprecation 2021-01-12 22:33:04 -08:00
Lalit Sharma 51f11ee630 Replacing deprecated tile_port syntax 2021-01-12 21:33:53 -08:00
Kevin Liao e06fdd0a48 add annotation to support soft_adder mode 2021-01-12 21:21:53 -08:00
Kevin Liao 489e370390 init 2021-01-11 21:11:12 -08:00
Tarachand Pagarani 01fabc65cc added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback 2020-12-21 07:13:38 -08:00
tangxifan e7fd8e7d92 [Arch] Fine-tune architecture file to be consistent in port naming as post-PnR netlist 2020-12-09 12:12:40 -07:00
tangxifan 6039ae92ca [Arch] Bug fix for buffering two-level routing multiplexers using custom cells 2020-12-05 19:37:34 -07:00
tangxifan 06731e092e [Arch] Patch reset port name to be consistent with post-PnR netlist 2020-12-02 13:46:40 -07:00
Laboratory for Nano Integrated Systems (LNIS) 07d1962051
Merge pull request #51 from lnis-uofu/xt_dev 
Add new architecture files which use custom cells based on Skywater HD library
 2020-12-01 22:16:49 -07:00
tangxifan b5abfdd994 [Arch] enable local encoders 2020-12-01 20:56:53 -07:00
tangxifan 3b6f3b0691 [Arch] Bug fix in new arch 2020-12-01 20:49:02 -07:00
tangxifan 454ea09dc4 [Arch] Add architecture using custom cells 2020-12-01 20:19:22 -07:00
Laboratory for Nano Integrated Systems (LNIS) f4397e1656
Merge pull request #47 from LNIS-Projects/xt_dev 
Bug fix in the arch port naming
 2020-11-30 18:23:38 -07:00
tangxifan be9399a016 [Arch] Bug fix in the arch port naming: prog_reset is a reserved word in OpenFPGA 2020-11-30 17:58:56 -07:00
Tarachand Pagarani 9f7fb8a34d modify carry chain to change output mux 2020-11-30 07:08:09 -08:00
tangxifan 14c21378b8 [Arch] Add new architecture using reset and softadder 2020-11-27 18:12:06 -07:00
tangxifan efab96d2dd [Arch] Bug fix in softadder architecture 2020-11-27 16:36:31 -07:00
tangxifan 295df663bb [Arch] Add arch variant with soft adders 2020-11-27 15:57:05 -07:00
tangxifan c424c3d9a6 [Arch] Add a new variant with reset signals to FFs 2020-11-27 14:41:53 -07:00
tangxifan 864ed26c9a [Arch] Merge latest arch from QuickLogic team on AP3 device using VPR routing architecture 2020-11-27 10:11:40 -07:00
tangxifan a92b9ce482 [Arch] Test Quicklogic test architecture 2020-11-25 15:58:50 -07:00
tangxifan 3ae41e2207 [Arch] Double checked I/O default direction set up in OpenFPGA architecture. Add comments for this point 2020-11-18 11:56:22 -07:00
tangxifan 1bfc793600 [Arch] Bug fix due to the use of embedded I/O cell 2020-11-17 19:55:04 -07:00
tangxifan 6a27eca809 [Arch] Update arch to use digital I/O circuitry 2020-11-17 19:34:58 -07:00
tangxifan be33082faf [Arch] Remove out-of-data architectures 2020-11-13 09:50:45 -07:00
tangxifan bbf871d22a [Arch] Limit shift register chain only to columns of clbs 2020-11-13 09:39:59 -07:00
tangxifan 5d3b08ada4 [Arch] Rename ports to be consistent with backend scripts and remove shift-register chain across fabric 2020-11-13 09:24:57 -07:00
tangxifan 7dafb7e3b2 [Arch] Use global clock from tile port in caravel architecture 2020-11-11 19:43:24 -07:00
tangxifan 11ee81f8c4 [Arch] Bug fix in the caravel arch 2020-11-08 14:25:38 -07:00
tangxifan 8d84d83eab [Arch] Use single-output DFF to further compress area 2020-11-06 11:47:31 -07:00
tangxifan 6b474ce422 [Arch] Patch openfpga arch for new syntax on I/O 2020-11-05 10:37:37 -07:00
tangxifan a25b8252f3 [Arch] Add openfpga arch template for the caravel 2020-11-05 10:20:54 -07:00
tangxifan 1264054cab [Arch] Bug fix in netlist path 2020-11-03 09:57:25 -07:00
tangxifan 48d8f8b664 [Arch] Same patch on the scff on another arch 2020-11-03 09:54:30 -07:00
tangxifan 533a6ab90f [Arch] Use an exact fit scan-chain flip-flop in the architectures 2020-11-03 09:53:16 -07:00
tangxifan b5c781f555 [Arch] Patch the HDL netlist name to differetiate between cell types 2020-11-03 09:17:22 -07:00