tangxifan
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40ca8dfbe3
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[Arch] Update architecture files to use the wrapper files
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2020-11-03 09:14:47 -07:00 |
tangxifan
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c26f8a5aac
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[Arch] Add architecture files for embedded FPGA IP
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2020-11-02 19:55:40 -07:00 |
tangxifan
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bff4fdfdc1
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[Arch] Update pin equivalence for the non-LR non-adder k4 arch
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2020-11-02 11:27:44 -07:00 |
tangxifan
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23ac6af11f
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[Arch] Bug fix on the wrong verilog netlist path
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2020-11-01 15:45:41 -07:00 |
tangxifan
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eaf5ba6074
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[Arch] Add openfpga arch for non-adder k4 vpr arch
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2020-10-24 11:44:41 -06:00 |
tangxifan
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5e6a6d1e53
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[Architecture] Add a set of openfpga architectures using different Skywater Foundry standard cells
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2020-10-14 09:11:05 -06:00 |
tangxifan
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14050bba26
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[Architecture] Add OpenFPGA architecture which is binded to the open-source ms sclib
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2020-10-10 19:16:35 -06:00 |
tangxifan
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cee0fa601e
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[Documentation] Add README for subdirectories
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2020-10-09 22:36:43 -06:00 |
tangxifan
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8b5a17457c
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[Architecture] bug fix in openfpga arch
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2020-10-09 20:30:51 -06:00 |
tangxifan
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0053c57954
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[Arch] Update architecture file
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2020-10-09 18:32:31 -06:00 |
tangxifan
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069c36cbfc
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[Architecture] Create template architecture for openfpga
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2020-10-09 17:28:14 -06:00 |