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431 Commits 16 Branches 1 Tag 1.8 GiB
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431 Commits

Author SHA1 Message Date
tangxifan 4e9b07125e [Script] Bug fix 2020-11-28 15:01:09 -07:00
tangxifan d70bcbb7ca [Doc] Add README for Modelsim workspace 2020-11-28 14:59:26 -07:00
tangxifan d3b1562fa2 [Testbench] Rename top-level module to be compatible to Modelsim task run scripts 2020-11-28 14:55:17 -07:00
tangxifan ee92b15f0e [Script] Bug fix in modelsim task-run script 2020-11-28 14:50:39 -07:00
tangxifan 2380783808 [Testbench] Remove post pnr testbenches that can be auto-generated 2020-11-28 14:46:27 -07:00
tangxifan 8374fcfd4e [Script] Rectify output messages 2020-11-28 14:41:48 -07:00
tangxifan 396988b1b6 [Script] Now testbench generator requires a specific dir name 2020-11-28 14:39:18 -07:00
tangxifan e88a33831c [Testbench] Update scripts to rename top-level module for post-PnR testbenches 2020-11-28 14:29:56 -07:00
tangxifan 1b7b247097 [Testbench] Rename to be compatible with Modelsim run scripts 2020-11-28 14:25:55 -07:00
tangxifan 8c44532e4e [Script] Add python script to run all the testbenches in a given repo 2020-11-28 14:24:27 -07:00
tangxifan 56cbe48ad6 [Script] Disable debugging log in single Modelsim verification task 2020-11-28 13:53:14 -07:00
tangxifan 9c7ec9bd61 [Script] Now python script for post-pnr Modelsim simulation works 2020-11-28 13:00:21 -07:00
tangxifan a9b94d4303 [Testbench] Update top-level module name for post PnR testbenches 2020-11-28 12:59:59 -07:00
tangxifan b2ebac3b23 [Testbench] Rename post-PnR testbenches to ease modelsim batch jobs 2020-11-28 11:14:34 -07:00
tangxifan 0c9953a26e [Testbench] Update post-PnR testbenches to synchornize with latest netlist 2020-11-28 11:09:55 -07:00
tangxifan 0f0133951c [Script] Update modelsim script for post-PnR verification 2020-11-28 11:07:39 -07:00
tangxifan f435d80dcc
Merge pull request #41 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-11-27 22:55:45 -07:00
Ganesh Gore 66d09da857 [FPGA1212_v1] Updated the PostPnR Netlist and PnR Files 2020-11-27 22:11:51 -07:00
Ganesh Gore ce4a6f72f5 [FPGA1212_v1] Updated the task and PrePNR Verilog netlist 2020-11-27 22:08:16 -07:00
Ganesh Gore da097413b0 [Cleanup] Removed buggy hierarchical flow files 2020-11-27 22:00:43 -07:00
Laboratory for Nano Integrated Systems (LNIS) 4c8e94722c
Merge pull request #40 from LNIS-Projects/xt_dev 
New Architecture: Support both Reset pins in FFs and Soft Adders
 2020-11-27 20:00:05 -07:00
tangxifan c7ea3f3936 [Arch] Bug fix in the arch with reset and soft adder 2020-11-27 19:54:31 -07:00
tangxifan 6a12cdbad1 [Script] Add task run for the architecture with both reset and soft adders 2020-11-27 18:15:05 -07:00
tangxifan 14c21378b8 [Arch] Add new architecture using reset and softadder 2020-11-27 18:12:06 -07:00
Ganesh Gore 5be185e7a5 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-11-27 17:51:51 -07:00
Laboratory for Nano Integrated Systems (LNIS) 9102b7ec5e
Merge pull request #39 from LNIS-Projects/xt_dev 
New Architecture: Support Carry Adders which are Implemented by LUTs
 2020-11-27 16:41:57 -07:00
tangxifan efab96d2dd [Arch] Bug fix in softadder architecture 2020-11-27 16:36:31 -07:00
tangxifan e5a66dd47f [Script] Add task run for softadder architecture 2020-11-27 16:14:14 -07:00
tangxifan 31dcd4a17f [HDL] Add a wrapper for HD MUX2 cell required by carry logic 2020-11-27 16:01:27 -07:00
tangxifan 295df663bb [Arch] Add arch variant with soft adders 2020-11-27 15:57:05 -07:00
Laboratory for Nano Integrated Systems (LNIS) 5bbb3959ca
Merge pull request #38 from LNIS-Projects/xt_dev 
Misc Updates: New Architecture and Verification Scripts
 2020-11-27 15:22:48 -07:00
tangxifan 28c8dba87b [Script] Bug fix in task configuration files 2020-11-27 15:05:35 -07:00
tangxifan f27424c803 [Arch] Bug fix in the architecture using reset 2020-11-27 15:04:19 -07:00
tangxifan 91edfb8e02 [Script] Add task run for the architecture with reset 2020-11-27 14:45:00 -07:00
tangxifan c424c3d9a6 [Arch] Add a new variant with reset signals to FFs 2020-11-27 14:41:53 -07:00
tangxifan 41745229d9 [Script] Add example script to run HDL simulations 2020-11-27 14:27:20 -07:00
tangxifan 42e188732d [Testbench] Use python to auto-generate the post-pnr testbenches 2020-11-27 14:17:56 -07:00
tangxifan 5ae1424754 [Script] Bug fix in outputting post-pnr testbenches 2020-11-27 14:17:33 -07:00
tangxifan 8c6d122fa3 [Testbench] Remove out-of-date testbenches 2020-11-27 12:30:47 -07:00
tangxifan 5947308e21 [Script] Add batch Python script for converting all the pre-PnR testbenches to post-PnR testbenches 2020-11-27 12:25:08 -07:00
tangxifan b82dbd1a05 [Doc] Update README for python script 2020-11-27 10:29:32 -07:00
tangxifan 864ed26c9a [Arch] Merge latest arch from QuickLogic team on AP3 device using VPR routing architecture 2020-11-27 10:11:40 -07:00
Laboratory for Nano Integrated Systems (LNIS) 5bb0db4e91
Merge pull request #37 from LNIS-Projects/xt_dev 
Python Script to Convert pre-PnR Verilog Testbench to post-PnR Verilog Testbench
 2020-11-26 20:53:21 -07:00
tangxifan feafc46465 [Script] Add python script to convert pre-PnR testbench to post-PnR testbench 2020-11-26 20:47:29 -07:00
tangxifan 2d30c10403 [Script] Now batch task run will error out in the first failed task 2020-11-26 18:30:01 -07:00
tangxifan c237500588 [Script] Remove signal initialization from testbench generator 2020-11-26 18:23:26 -07:00
Laboratory for Nano Integrated Systems (LNIS) 82c00eda30
Merge pull request #36 from LNIS-Projects/xt_dev 
Critical Patch on VPR Arch for Shift Register Implementation
 2020-11-25 20:14:43 -07:00
tangxifan ba17de5509 [Doc] Add description about operating modes of Logic Elements 2020-11-25 17:43:35 -07:00
tangxifan a4f6c34466 [Doc] Add images for multi-mode logic element architecture 2020-11-25 17:17:07 -07:00
tangxifan 0fa3604b6c [Arch] Update arch to enable more routability in shift register mode 2020-11-25 17:04:08 -07:00