mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #36 from LNIS-Projects/xt_dev
Critical Patch on VPR Arch for Shift Register Implementation
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS)
GitHub
commit
82c00eda30
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@ -1,2 +1,3 @@
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*.gds filter=lfs diff=lfs merge=lfs -text
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*.spef filter=lfs diff=lfs merge=lfs -text
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*.v filter=lfs diff=lfs merge=lfs -text
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@ -0,0 +1,237 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k4_frac_cc_sky130nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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- Skywater 130nm PDK
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- circuit models are binded to the opensource skywater
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foundry middle-speed (ms) standard cell library
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
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<design_technology type="cmos" topology="buffer" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="Y" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<!-- Define a circuit model for the standard cell MUX2
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OpenFPGA requires the following truth table for the MUX2
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When the select signal sel is enabled, the first input, i.e., in0
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will be propagated to the output, i.e., out
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If your standard cell provider does not offer the exact truth table,
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you can simply swap the inputs as shown in the example below
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-->
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<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
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<design_technology type="cmos" topology="MUX2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in0" lib_name="A1" size="1"/>
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<port type="input" prefix="in1" lib_name="A0" size="1"/>
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<port type="input" prefix="sel" lib_name="S" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="sky130_fd_sc_hd__dfxtp_1" prefix="sky130_fd_sc_hd__dfxtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
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<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
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<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
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<port type="input" prefix="in" size="4"/>
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<port type="output" prefix="lut3_out" size="1" lut_frac_level="3" lut_output_mask="1"/>
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<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="16"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="sky130_fd_sc_hd__dfxtp_1" prefix="sky130_fd_sc_hd__dfxtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
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<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
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<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
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<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
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<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="LOGIC_VDD" prefix="LOGIC_VDD" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="output" prefix="a" lib_name="Y" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="LOGIC_GND" prefix="LOGIC_GND" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="output" prefix="a" lib_name="Y" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" num_regions="1"/>
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</configuration_protocol>
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<connection_block>
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<switch name="routing" circuit_model_name="mux_tree_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="routing" circuit_model_name="mux_tree_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="hop4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<direct_connection>
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<direct name="adder_carry" circuit_model_name="direct_interc"/>
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</direct_connection>
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<tile_annotations>
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<global_port name="clk" tile_port="SUPER_LOGIC_CELL.QCK" is_clock="true" default_val="0"/>
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</tile_annotations>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="IO" physical_mode_name="PHYSICAL" idle_mode_name="INPUT"/>
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<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
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<pb_type name="IO[PHYSICAL].PHYSICAL" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
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<pb_type name="IO[INPUT].INPUT" physical_pb_type_name="IO[PHYSICAL].PHYSICAL" mode_bits="1"/>
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<pb_type name="IO[OUTPUT].OUTPUT" physical_pb_type_name="IO[PHYSICAL].PHYSICAL" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
|
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<!-- physical mode will be the default mode if not specified -->
|
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<pb_type name="SUPER_LOGIC_CELL.LC" physical_mode_name="PHYSICAL"/>
|
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<pb_type name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
|
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<pb_type name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.ff" circuit_model_name="sky130_fd_sc_hd__dfxtp_1"/>
|
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<!-- BEGIN Binding operating pb_types in mode 'ble4' -->
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||||
<pb_type name="SUPER_LOGIC_CELL.LC[DEFAULT].DEFAULT.lut_part[VPR_LUT4].VPR_LUT4.lut_inst" physical_pb_type_name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.frac_logic.frac_lut4" mode_bits="0">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
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<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="SUPER_LOGIC_CELL.LC[DEFAULT].DEFAULT.ff" physical_pb_type_name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.ff"/>
|
||||
<!-- END Binding operating pb_types in mode 'ble4' -->
|
||||
|
||||
<!-- physical pb_type binding in complex block LOGIC1 -->
|
||||
<pb_type name="LOGIC_1.logic_1" circuit_model_name="LOGIC_VDD"/>
|
||||
<!-- physical pb_type binding in complex block LOGIC0 -->
|
||||
<pb_type name="LOGIC_0.gnd" circuit_model_name="LOGIC_GND"/>
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -396,18 +396,21 @@
|
|||
<direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
|
||||
<direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
|
||||
<direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
|
||||
<direct name="direct6" input="frac_logic.out[1:1]" output="ff[1:1].D"/>
|
||||
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
|
||||
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
|
||||
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
|
||||
</mux>
|
||||
<mux name="mux2" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
|
||||
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
|
||||
</mux>
|
||||
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
|
||||
</mux>
|
||||
<mux name="mux3" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
|
||||
|
|
@ -551,6 +554,7 @@
|
|||
<mode name="shift_register">
|
||||
<pb_type name="shift_reg" num_pb="1">
|
||||
<input name="reg_in" num_pins="1"/>
|
||||
<output name="ff_out" num_pins="2"/>
|
||||
<output name="reg_out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
|
||||
|
|
@ -564,13 +568,16 @@
|
|||
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
|
||||
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
|
||||
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
|
||||
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
|
||||
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
|
||||
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.reg_in" output="shift_reg.reg_in"/>
|
||||
<direct name="direct2" input="shift_reg.reg_out" output="fle.reg_out"/>
|
||||
<direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
|
||||
<direct name="direct3" input="shift_reg.ff_out" output="fle.out"/>
|
||||
<direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Define shift register end -->
|
||||
|
|
|
|||
|
|
@ -0,0 +1,555 @@
|
|||
<?xml version="1.0" ?>
|
||||
<architecture name="QL745A" xmlns:xi="http://www.w3.org/2001/XInclude">
|
||||
<models>
|
||||
<model name="IO_MACRO">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="openfpga_ff">
|
||||
<input_ports>
|
||||
<port clock="QCK" name="D"/>
|
||||
<port is_clock="1" name="QCK"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port clock="QCK" name="CQZ"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="LUT4">
|
||||
<input_ports>
|
||||
<port combinational_sink_ports="O" name="I0"/>
|
||||
<port combinational_sink_ports="O" name="I1"/>
|
||||
<port combinational_sink_ports="O" name="I2"/>
|
||||
<port combinational_sink_ports="O" name="I3"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="O"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="logic_1">
|
||||
<input_ports/>
|
||||
<output_ports>
|
||||
<port name="a"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="logic_0">
|
||||
<input_ports/>
|
||||
<output_ports>
|
||||
<port name="a"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<tile capacity="8" name="IO">
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="top">
|
||||
IO.OQI
|
||||
</loc>
|
||||
<loc side="right">
|
||||
IO.IQZ
|
||||
</loc>
|
||||
</pinlocations>
|
||||
<fc in_type="frac" in_val="0.50" out_type="frac" out_val="0.25"/>
|
||||
<input equivalent="none" name="OQI" num_pins="1"/>
|
||||
<output equivalent="none" name="IQZ" num_pins="1"/>
|
||||
<equivalent_sites>
|
||||
<site pb_type="IO" pin_mapping="custom">
|
||||
<direct from="IO.IQZ" to="IO.inpad"/>
|
||||
<direct from="IO.OQI" to="IO.outpad"/>
|
||||
</site>
|
||||
</equivalent_sites>
|
||||
</tile>
|
||||
<!-- Super Logic Cluster tile -->
|
||||
<tile area="3900" name="SUPER_LOGIC_CELL">
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="top">
|
||||
SUPER_LOGIC_CELL.L0I
|
||||
SUPER_LOGIC_CELL.L1I
|
||||
SUPER_LOGIC_CELL.L2I
|
||||
SUPER_LOGIC_CELL.L3I
|
||||
SUPER_LOGIC_CELL.L4I
|
||||
SUPER_LOGIC_CELL.L5I
|
||||
SUPER_LOGIC_CELL.L6I
|
||||
SUPER_LOGIC_CELL.L7I
|
||||
SUPER_LOGIC_CELL.CI
|
||||
SUPER_LOGIC_CELL.QCK
|
||||
</loc>
|
||||
<loc side="right">
|
||||
SUPER_LOGIC_CELL.FZ
|
||||
SUPER_LOGIC_CELL.AQZ
|
||||
</loc>
|
||||
<loc side="bottom">
|
||||
SUPER_LOGIC_CELL.CO
|
||||
</loc>
|
||||
</pinlocations>
|
||||
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="0.25"/>
|
||||
<clock name="QCK" num_pins="1"/>
|
||||
<output equivalent="none" name="AQZ" num_pins="8"/>
|
||||
<output equivalent="none" name="FZ" num_pins="8"/>
|
||||
<output name="CO" num_pins="1"/>
|
||||
<!-- Carry output from the last logic cell -->
|
||||
<input name="CI" num_pins="1"/>
|
||||
<!-- Carry input to the 1st logic cell -->
|
||||
<input equivalent="none" name="L7I" num_pins="4"/>
|
||||
<input equivalent="none" name="L6I" num_pins="4"/>
|
||||
<input equivalent="none" name="L5I" num_pins="4"/>
|
||||
<input equivalent="none" name="L4I" num_pins="4"/>
|
||||
<input equivalent="none" name="L3I" num_pins="4"/>
|
||||
<input equivalent="none" name="L2I" num_pins="4"/>
|
||||
<input equivalent="none" name="L1I" num_pins="4"/>
|
||||
<input equivalent="none" name="L0I" num_pins="4"/>
|
||||
<!-- Data inputs to each logic cell -->
|
||||
<equivalent_sites>
|
||||
<site pb_type="SUPER_LOGIC_CELL" pin_mapping="custom">
|
||||
<direct from="SUPER_LOGIC_CELL.L0I" to="SUPER_LOGIC_CELL.L0I"/>
|
||||
<direct from="SUPER_LOGIC_CELL.L1I" to="SUPER_LOGIC_CELL.L1I"/>
|
||||
<direct from="SUPER_LOGIC_CELL.L2I" to="SUPER_LOGIC_CELL.L2I"/>
|
||||
<direct from="SUPER_LOGIC_CELL.L3I" to="SUPER_LOGIC_CELL.L3I"/>
|
||||
<direct from="SUPER_LOGIC_CELL.L4I" to="SUPER_LOGIC_CELL.L4I"/>
|
||||
<direct from="SUPER_LOGIC_CELL.L5I" to="SUPER_LOGIC_CELL.L5I"/>
|
||||
<direct from="SUPER_LOGIC_CELL.L6I" to="SUPER_LOGIC_CELL.L6I"/>
|
||||
<direct from="SUPER_LOGIC_CELL.L7I" to="SUPER_LOGIC_CELL.L7I"/>
|
||||
<direct from="SUPER_LOGIC_CELL.CI" to="SUPER_LOGIC_CELL.CI"/>
|
||||
<direct from="SUPER_LOGIC_CELL.CO" to="SUPER_LOGIC_CELL.CO"/>
|
||||
<direct from="SUPER_LOGIC_CELL.FZ" to="SUPER_LOGIC_CELL.FZ"/>
|
||||
<direct from="SUPER_LOGIC_CELL.AQZ" to="SUPER_LOGIC_CELL.AQZ"/>
|
||||
<direct from="SUPER_LOGIC_CELL.QCK" to="SUPER_LOGIC_CELL.QCK"/>
|
||||
</site>
|
||||
</equivalent_sites>
|
||||
</tile>
|
||||
<tile capacity="1" name="TL-VCC">
|
||||
<switchbox_locations pattern="all"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="right">TL-VCC.VCC</loc>
|
||||
</pinlocations>
|
||||
<fc in_type="frac" in_val="0.50" out_type="frac" out_val="0.25"/>
|
||||
<equivalent_sites>
|
||||
<site pb_type="LOGIC_1" pin_mapping="custom">
|
||||
<direct from="TL-VCC.VCC" to="LOGIC_1.a"/>
|
||||
</site>
|
||||
</equivalent_sites>
|
||||
<output name="VCC" num_pins="1"/>
|
||||
</tile>
|
||||
<tile capacity="1" name="TL-GND">
|
||||
<switchbox_locations pattern="all"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="right">TL-GND.GND</loc>
|
||||
</pinlocations>
|
||||
<fc in_type="frac" in_val="0.50" out_type="frac" out_val="0.25"/>
|
||||
<equivalent_sites>
|
||||
<site pb_type="LOGIC_0" pin_mapping="custom">
|
||||
<direct from="TL-GND.GND" to="LOGIC_0.a"/>
|
||||
</site>
|
||||
</equivalent_sites>
|
||||
<output name="GND" num_pins="1"/>
|
||||
</tile>
|
||||
</tiles>
|
||||
<layout>
|
||||
<fixed_layout height="12" name="ql-ap3-8x8" width="12">
|
||||
<!-- Fill the entire grid with empty tiles -->
|
||||
<region endx="W-1" endy="H-1" priority="1" startx="0" starty="0" type="EMPTY"/>
|
||||
<!-- Fill with 'SLC' -->
|
||||
<region endx="W-3" endy="H-3" priority="10" startx="2" starty="2" type="SUPER_LOGIC_CELL"/>
|
||||
<!-- Top IOs -->
|
||||
<region endx="W-3" endy="1" priority="20" startx="2" starty="1" type="IO"/>
|
||||
<!-- Left IOs -->
|
||||
<region endx="1" endy="H-3" priority="20" startx="1" starty="2" type="IO"/>
|
||||
<!-- Bottom IOs -->
|
||||
<region endx="W-3" endy="H-2" priority="20" startx="2" starty="H-2" type="IO"/>
|
||||
<!-- Right IOs -->
|
||||
<region endx="W-2" endy="H-3" priority="20" startx="W-2" starty="2" type="IO"/>
|
||||
<!-- Const sources -->
|
||||
<single priority="100" type="TL-VCC" x="1" y="1"/>
|
||||
<single priority="100" type="TL-GND" x="1" y="H-2"/>
|
||||
</fixed_layout>
|
||||
</layout>
|
||||
<device>
|
||||
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<switch_block fs="3" type="wilton"/>
|
||||
<connection_block input_switch_name="routing"/>
|
||||
<default_fc in_type="frac" in_val="0.50" out_type="frac" out_val="0.25"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<switch Cin="0.0" Cinternal="0.0" Cout="0.0" R="0.0" Tdel="1e-10" buf_size="27.645901" mux_trans_size="2.630740" name="routing" type="mux"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<segment Cmetal="22.5e-15" Rmetal="1e-12" freq="1.000000" length="4" name="hop4" type="unidir">
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
<mux name="routing"/>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<directlist>
|
||||
<direct from_pin="SUPER_LOGIC_CELL.CO" name="adder_carry" to_pin="SUPER_LOGIC_CELL.CI" x_offset="0" y_offset="-1" z_offset="0"/>
|
||||
</directlist>
|
||||
<complexblocklist>
|
||||
<pb_type name="IO">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<mode name="PHYSICAL">
|
||||
<pb_type name="PHYSICAL" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<pb_type blif_model=".subckt IO_MACRO" name="macro" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="macro.inpad" name="PHYSICAL-inpad" output="PHYSICAL.inpad"/>
|
||||
<direct input="PHYSICAL.outpad" name="macro-outpad" output="macro.outpad"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="PHYSICAL.inpad" name="IO-inpad" output="IO.inpad"/>
|
||||
<direct input="IO.outpad" name="PHYSICAL-outpad" output="PHYSICAL.outpad"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="INPUT">
|
||||
<pb_type name="INPUT" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<pb_type blif_model=".input" name="i_pad" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="i_pad.inpad" name="INPUT-inpad" output="INPUT.inpad"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="IO.outpad" name="INPUT-outpad" output="INPUT.outpad"/>
|
||||
<direct input="INPUT.inpad" name="IO-inpad" output="IO.inpad"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="OUTPUT">
|
||||
<pb_type name="OUTPUT" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<pb_type blif_model=".output" name="o_pad" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="OUTPUT.outpad" name="o_pad-outpad" output="o_pad.outpad"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="OUTPUT.inpad" name="IO-inpad" output="IO.inpad"/>
|
||||
<direct input="IO.outpad" name="OUTPUT-outpad" output="OUTPUT.outpad"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<pb_type name="SUPER_LOGIC_CELL">
|
||||
<clock name="QCK" num_pins="1"/>
|
||||
<input name="CI" num_pins="1"/>
|
||||
<input name="L0I" num_pins="4"/>
|
||||
<input name="L1I" num_pins="4"/>
|
||||
<input name="L2I" num_pins="4"/>
|
||||
<input name="L3I" num_pins="4"/>
|
||||
<input name="L4I" num_pins="4"/>
|
||||
<input name="L5I" num_pins="4"/>
|
||||
<input name="L6I" num_pins="4"/>
|
||||
<input name="L7I" num_pins="4"/>
|
||||
<output name="AQZ" num_pins="8"/>
|
||||
<output name="CO" num_pins="1"/>
|
||||
<output name="FZ" num_pins="8"/>
|
||||
<pb_type name="LC" num_pb="8">
|
||||
<input name="CI" num_pins="1"/>
|
||||
<input name="LI" num_pins="4"/>
|
||||
<input name="QCK" num_pins="1"/>
|
||||
<output name="AQZ" num_pins="1"/>
|
||||
<output name="CO" num_pins="1"/>
|
||||
<output name="FZ" num_pins="1"/>
|
||||
<mode name="PHYSICAL" disabled_in_pack="true">
|
||||
<pb_type name="PHYSICAL" num_pb="1">
|
||||
<input name="CI" num_pins="1"/>
|
||||
<input name="LI" num_pins="4"/>
|
||||
<output name="AQZ" num_pins="1"/>
|
||||
<output name="CO" num_pins="1"/>
|
||||
<output name="FZ" num_pins="1"/>
|
||||
<clock name="QCK" num_pins="1"/>
|
||||
<pb_type name="frac_logic" num_pb="1">
|
||||
<input name="LI" num_pins="4"/>
|
||||
<input name="CI" num_pins="1"/>
|
||||
<output name="O" num_pins="1"/>
|
||||
<output name="CO" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="frac_lut4" blif_model=".subckt LUT4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="lut3_out" num_pins="1"/>
|
||||
<output name="lut4_out" num_pins="1"/>
|
||||
<delay_constant in_port="frac_lut4.in" max="1e-10" out_port="frac_lut4.lut3_out"/>
|
||||
<delay_constant in_port="frac_lut4.in" max="1e-10" out_port="frac_lut4.lut4_out"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="frac_logic.LI[0]" output="frac_lut4.in[0]" />
|
||||
<direct name="direct2" input="frac_logic.LI[1]" output="frac_lut4.in[1]" />
|
||||
<mux name="i2_ci" input="frac_logic.LI[2] frac_logic.CI" output="frac_lut4.in[2]"/>
|
||||
<direct name="direct3" input="frac_logic.LI[3]" output="frac_lut4.in[3]" />
|
||||
<direct name="direct4" input="frac_lut4.lut4_out" output="frac_logic.O" />
|
||||
<direct name="direct4" input="frac_lut4.lut3_out" output="frac_logic.CO" />
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
|
||||
<pb_type name="ff" blif_model=".subckt openfpga_ff" num_pb="1">
|
||||
<clock name="QCK" num_pins="1"/>
|
||||
<input name="D" num_pins="1"/>
|
||||
<output name="CQZ" num_pins="1"/>
|
||||
<T_clock_to_Q clock="QCK" max="1e-10" port="ff.CQZ"/>
|
||||
<T_setup clock="QCK" port="ff.D" value="1e-10"/>
|
||||
<T_hold clock="QCK" port="ff.D" value="1e-10"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct_LI0" input="PHYSICAL.LI[0]" output="frac_logic.LI[0]" />
|
||||
<direct name="direct_LI1" input="PHYSICAL.LI[1]" output="frac_logic.LI[1]" />
|
||||
<direct name="direct_LI2" input="PHYSICAL.LI[2]" output="frac_logic.LI[2]" />
|
||||
<direct name="direct_LI3" input="PHYSICAL.LI[3]" output="frac_logic.LI[3]" />
|
||||
<direct name="direct_CI" input="PHYSICAL.CI" output="frac_logic.CI" />
|
||||
<direct name="direct_QCK" input="PHYSICAL.QCK" output="ff.QCK" />
|
||||
<mux name="lut_qdi" input="frac_logic.O PHYSICAL.LI[3]" output="ff.D"/>
|
||||
<direct name="direct_AQZ" input="ff.CQZ" output="PHYSICAL.AQZ" />
|
||||
<direct name="direct_FZ" input="frac_logic.O" output="PHYSICAL.FZ" />
|
||||
<direct name="direct_CO" input="frac_logic.CO" output="PHYSICAL.CO" />
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="PHYSICAL.AQZ" name="LC-AQZ" output="LC.AQZ"/>
|
||||
<direct input="PHYSICAL.CO" name="LC-CO" output="LC.CO"/>
|
||||
<direct input="PHYSICAL.FZ" name="LC-FZ" output="LC.FZ"/>
|
||||
<direct input="LC.CI" name="PHYSICAL-CI" output="PHYSICAL.CI"/>
|
||||
<direct input="LC.LI" name="PHYSICAL-LI" output="PHYSICAL.LI"/>
|
||||
<direct input="LC.QCK" name="PHYSICAL-QCK" output="PHYSICAL.QCK"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
|
||||
<mode name="DEFAULT">
|
||||
<pb_type name="DEFAULT" num_pb="1">
|
||||
<input name="CI" num_pins="1"/>
|
||||
<input name="LI" num_pins="4"/>
|
||||
<input name="QCK" num_pins="1"/>
|
||||
<output name="AQZ" num_pins="1"/>
|
||||
<output name="CO" num_pins="1"/>
|
||||
<output name="FZ" num_pins="1"/>
|
||||
<pb_type blif_model=".subckt openfpga_ff" name="ff" num_pb="1">
|
||||
<clock name="QCK" num_pins="1"/>
|
||||
<input name="D" num_pins="1"/>
|
||||
<output name="CQZ" num_pins="1"/>
|
||||
<T_clock_to_Q clock="QCK" max="1e-10" port="ff.CQZ"/>
|
||||
<T_setup clock="QCK" port="ff.D" value="1e-10"/>
|
||||
<T_hold clock="QCK" port="ff.D" value="1e-10"/>
|
||||
<metadata>
|
||||
<meta name="fasm_prefix">BLK2REG</meta>
|
||||
<meta name="fasm_features"/>
|
||||
</metadata>
|
||||
</pb_type>
|
||||
<pb_type name="lut_part" num_pb="1">
|
||||
<input name="LI" num_pins="4"/>
|
||||
<output name="FZ" num_pins="1"/>
|
||||
<mode name="VPR_LUT4">
|
||||
<pb_type name="VPR_LUT4" num_pb="1">
|
||||
<input name="LI" num_pins="4"/>
|
||||
<output name="FZ" num_pins="1"/>
|
||||
<pb_type name="lut_inst" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<pb_type blif_model=".names" class="lut" name="lut" num_pb="1">
|
||||
<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<delay_matrix in_port="lut.in" out_port="lut.out" type="max">
|
||||
1e-10 1e-10 1e-10 1e-10
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="lut_inst.in[0]" name="lut-in[0]" output="lut.in[0]"/>
|
||||
<direct input="lut_inst.in[1]" name="lut-in[1]" output="lut.in[1]"/>
|
||||
<direct input="lut_inst.in[2]" name="lut-in[2]" output="lut.in[2]"/>
|
||||
<direct input="lut_inst.in[3]" name="lut-in[3]" output="lut.in[3]"/>
|
||||
<direct input="lut.out" name="lut_inst-out" output="lut_inst.out"/>
|
||||
</interconnect>
|
||||
<metadata>
|
||||
<meta name="fasm_prefix">LUT4</meta>
|
||||
<meta name="fasm_type">LUT</meta>
|
||||
<meta name="fasm_lut">INIT[15:0] = lut</meta>
|
||||
</metadata>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="lut_inst.out" name="VPR_LUT4-FZ" output="VPR_LUT4.FZ">
|
||||
<pack_pattern in_port="lut_inst.out" name="pack-VPR_LUT_to_FF" out_port="VPR_LUT4.FZ"/>
|
||||
</direct>
|
||||
<direct input="VPR_LUT4.LI[0]" name="lut_inst-in[0]" output="lut_inst.in[0]"/>
|
||||
<direct input="VPR_LUT4.LI[1]" name="lut_inst-in[1]" output="lut_inst.in[1]"/>
|
||||
<direct input="VPR_LUT4.LI[2]" name="lut_inst-in[2]" output="lut_inst.in[2]"/>
|
||||
<direct input="VPR_LUT4.LI[3]" name="lut_inst-in[3]" output="lut_inst.in[3]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="lut_part.LI" name="VPR_LUT4-LI" output="VPR_LUT4.LI"/>
|
||||
<direct input="VPR_LUT4.FZ" name="lut_part-FZ" output="lut_part.FZ"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!--mode name="LUT4">
|
||||
<pb_type name="LUT4" num_pb="1">
|
||||
<input name="LI" num_pins="4"/>
|
||||
<output name="FZ" num_pins="1"/>
|
||||
<pb_type blif_model=".subckt LUT4" name="lut_inst" num_pb="1">
|
||||
<input name="I0" num_pins="1"/>
|
||||
<input name="I1" num_pins="1"/>
|
||||
<input name="I2" num_pins="1"/>
|
||||
<input name="I3" num_pins="1"/>
|
||||
<output name="O" num_pins="1"/>
|
||||
<delay_constant in_port="lut_inst.I0" max="1e-10" out_port="lut_inst.O"/>
|
||||
<delay_constant in_port="lut_inst.I1" max="1e-10" out_port="lut_inst.O"/>
|
||||
<delay_constant in_port="lut_inst.I2" max="1e-10" out_port="lut_inst.O"/>
|
||||
<delay_constant in_port="lut_inst.I3" max="1e-10" out_port="lut_inst.O"/>
|
||||
<metadata>
|
||||
<meta name="fasm_prefix">LUT4</meta>
|
||||
<meta name="fasm_params">INIT[15:0]=INIT</meta>
|
||||
</metadata>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="lut_inst.O" name="LUT4-FZ" output="LUT4.FZ">
|
||||
<pack_pattern in_port="lut_inst.O" name="pack-LUT4_to_FF" out_port="LUT4.FZ"/>
|
||||
</direct>
|
||||
<direct input="LUT4.LI[0]" name="lut_inst-I0" output="lut_inst.I0"/>
|
||||
<direct input="LUT4.LI[1]" name="lut_inst-I1" output="lut_inst.I1"/>
|
||||
<direct input="LUT4.LI[2]" name="lut_inst-I2" output="lut_inst.I2"/>
|
||||
<direct input="LUT4.LI[3]" name="lut_inst-I3" output="lut_inst.I3"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="lut_part.LI" name="LUT4-LI" output="LUT4.LI"/>
|
||||
<direct input="LUT4.FZ" name="lut_part-FZ" output="lut_part.FZ"/>
|
||||
</interconnect>
|
||||
</mode-->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="ff.CQZ" name="DEFAULT-AQZ" output="DEFAULT.AQZ"/>
|
||||
<direct input="lut_part.FZ" name="DEFAULT-FZ" output="DEFAULT.FZ">
|
||||
<pack_pattern in_port="lut_part.FZ" name="pack-VPR_LUT_to_FF" out_port="DEFAULT.FZ"/>
|
||||
<!--pack_pattern in_port="lut_part.FZ" name="pack-LUT4_to_FF" out_port="DEFAULT.FZ"/-->
|
||||
</direct>
|
||||
<mux input="lut_part.FZ DEFAULT.LI[3]" name="cds_mux" output="ff.D">
|
||||
<metadata>
|
||||
<meta name="fasm_mux">
|
||||
lut_part.FZ : I0
|
||||
DEFAULT.LI[3] : I1
|
||||
</meta>
|
||||
<meta name="type">bel</meta>
|
||||
<meta name="subtype">routing</meta>
|
||||
</metadata>
|
||||
</mux>
|
||||
<direct input="DEFAULT.QCK" name="ff-QCK" output="ff.QCK"/>
|
||||
<direct input="DEFAULT.LI[0]" name="lut_part-LI[0]" output="lut_part.LI[0]"/>
|
||||
<direct input="DEFAULT.LI[1]" name="lut_part-LI[1]" output="lut_part.LI[1]"/>
|
||||
<direct input="DEFAULT.LI[2]" name="lut_part-LI[2]" output="lut_part.LI[2]"/>
|
||||
<direct input="DEFAULT.LI[3]" name="lut_part-LI[3]" output="lut_part.LI[3]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="LC.CI" name="DEFAULT-CI" output="DEFAULT.CI"/>
|
||||
<direct input="LC.LI" name="DEFAULT-LI" output="DEFAULT.LI"/>
|
||||
<direct input="LC.QCK" name="DEFAULT-QCK" output="DEFAULT.QCK"/>
|
||||
<direct input="DEFAULT.AQZ" name="LC-AQZ" output="LC.AQZ"/>
|
||||
<direct input="DEFAULT.CO" name="LC-CO" output="LC.CO"/>
|
||||
<direct input="DEFAULT.FZ" name="LC-FZ" output="LC.FZ"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<metadata>
|
||||
<meta name="fasm_prefix">LC0 LC1 LC2 LC3 LC4 LC5 LC6 LC7</meta>
|
||||
</metadata>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="SUPER_LOGIC_CELL.CI" name="LC[0]-CI" output="LC[0].CI"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L0I[0]" name="LC[0]-LI[0]" output="LC[0].LI[0]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L0I[1]" name="LC[0]-LI[1]" output="LC[0].LI[1]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L0I[2]" name="LC[0]-LI[2]" output="LC[0].LI[2]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L0I[3]" name="LC[0]-LI[3]" output="LC[0].LI[3]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.QCK" name="LC[0]-QCK" output="LC[0].QCK"/>
|
||||
<direct input="LC[0].CO" name="LC[1]-CI" output="LC[1].CI"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L1I[0]" name="LC[1]-LI[0]" output="LC[1].LI[0]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L1I[1]" name="LC[1]-LI[1]" output="LC[1].LI[1]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L1I[2]" name="LC[1]-LI[2]" output="LC[1].LI[2]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L1I[3]" name="LC[1]-LI[3]" output="LC[1].LI[3]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.QCK" name="LC[1]-QCK" output="LC[1].QCK"/>
|
||||
<direct input="LC[1].CO" name="LC[2]-CI" output="LC[2].CI"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L2I[0]" name="LC[2]-LI[0]" output="LC[2].LI[0]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L2I[1]" name="LC[2]-LI[1]" output="LC[2].LI[1]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L2I[2]" name="LC[2]-LI[2]" output="LC[2].LI[2]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L2I[3]" name="LC[2]-LI[3]" output="LC[2].LI[3]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.QCK" name="LC[2]-QCK" output="LC[2].QCK"/>
|
||||
<direct input="LC[2].CO" name="LC[3]-CI" output="LC[3].CI"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L3I[0]" name="LC[3]-LI[0]" output="LC[3].LI[0]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L3I[1]" name="LC[3]-LI[1]" output="LC[3].LI[1]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L3I[2]" name="LC[3]-LI[2]" output="LC[3].LI[2]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L3I[3]" name="LC[3]-LI[3]" output="LC[3].LI[3]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.QCK" name="LC[3]-QCK" output="LC[3].QCK"/>
|
||||
<direct input="LC[3].CO" name="LC[4]-CI" output="LC[4].CI"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L4I[0]" name="LC[4]-LI[0]" output="LC[4].LI[0]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L4I[1]" name="LC[4]-LI[1]" output="LC[4].LI[1]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L4I[2]" name="LC[4]-LI[2]" output="LC[4].LI[2]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L4I[3]" name="LC[4]-LI[3]" output="LC[4].LI[3]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.QCK" name="LC[4]-QCK" output="LC[4].QCK"/>
|
||||
<direct input="LC[4].CO" name="LC[5]-CI" output="LC[5].CI"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L5I[0]" name="LC[5]-LI[0]" output="LC[5].LI[0]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L5I[1]" name="LC[5]-LI[1]" output="LC[5].LI[1]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L5I[2]" name="LC[5]-LI[2]" output="LC[5].LI[2]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L5I[3]" name="LC[5]-LI[3]" output="LC[5].LI[3]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.QCK" name="LC[5]-QCK" output="LC[5].QCK"/>
|
||||
<direct input="LC[5].CO" name="LC[6]-CI" output="LC[6].CI"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L6I[0]" name="LC[6]-LI[0]" output="LC[6].LI[0]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L6I[1]" name="LC[6]-LI[1]" output="LC[6].LI[1]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L6I[2]" name="LC[6]-LI[2]" output="LC[6].LI[2]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L6I[3]" name="LC[6]-LI[3]" output="LC[6].LI[3]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.QCK" name="LC[6]-QCK" output="LC[6].QCK"/>
|
||||
<direct input="LC[6].CO" name="LC[7]-CI" output="LC[7].CI"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L7I[0]" name="LC[7]-LI[0]" output="LC[7].LI[0]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L7I[1]" name="LC[7]-LI[1]" output="LC[7].LI[1]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L7I[2]" name="LC[7]-LI[2]" output="LC[7].LI[2]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.L7I[3]" name="LC[7]-LI[3]" output="LC[7].LI[3]"/>
|
||||
<direct input="SUPER_LOGIC_CELL.QCK" name="LC[7]-QCK" output="LC[7].QCK"/>
|
||||
<direct input="LC[0].AQZ" name="SUPER_LOGIC_CELL-AQZ[0]" output="SUPER_LOGIC_CELL.AQZ[0]"/>
|
||||
<direct input="LC[1].AQZ" name="SUPER_LOGIC_CELL-AQZ[1]" output="SUPER_LOGIC_CELL.AQZ[1]"/>
|
||||
<direct input="LC[2].AQZ" name="SUPER_LOGIC_CELL-AQZ[2]" output="SUPER_LOGIC_CELL.AQZ[2]"/>
|
||||
<direct input="LC[3].AQZ" name="SUPER_LOGIC_CELL-AQZ[3]" output="SUPER_LOGIC_CELL.AQZ[3]"/>
|
||||
<direct input="LC[4].AQZ" name="SUPER_LOGIC_CELL-AQZ[4]" output="SUPER_LOGIC_CELL.AQZ[4]"/>
|
||||
<direct input="LC[5].AQZ" name="SUPER_LOGIC_CELL-AQZ[5]" output="SUPER_LOGIC_CELL.AQZ[5]"/>
|
||||
<direct input="LC[6].AQZ" name="SUPER_LOGIC_CELL-AQZ[6]" output="SUPER_LOGIC_CELL.AQZ[6]"/>
|
||||
<direct input="LC[7].AQZ" name="SUPER_LOGIC_CELL-AQZ[7]" output="SUPER_LOGIC_CELL.AQZ[7]"/>
|
||||
<direct input="LC[7].CO" name="SUPER_LOGIC_CELL-CO" output="SUPER_LOGIC_CELL.CO"/>
|
||||
<direct input="LC[0].FZ" name="SUPER_LOGIC_CELL-FZ[0]" output="SUPER_LOGIC_CELL.FZ[0]"/>
|
||||
<direct input="LC[1].FZ" name="SUPER_LOGIC_CELL-FZ[1]" output="SUPER_LOGIC_CELL.FZ[1]"/>
|
||||
<direct input="LC[2].FZ" name="SUPER_LOGIC_CELL-FZ[2]" output="SUPER_LOGIC_CELL.FZ[2]"/>
|
||||
<direct input="LC[3].FZ" name="SUPER_LOGIC_CELL-FZ[3]" output="SUPER_LOGIC_CELL.FZ[3]"/>
|
||||
<direct input="LC[4].FZ" name="SUPER_LOGIC_CELL-FZ[4]" output="SUPER_LOGIC_CELL.FZ[4]"/>
|
||||
<direct input="LC[5].FZ" name="SUPER_LOGIC_CELL-FZ[5]" output="SUPER_LOGIC_CELL.FZ[5]"/>
|
||||
<direct input="LC[6].FZ" name="SUPER_LOGIC_CELL-FZ[6]" output="SUPER_LOGIC_CELL.FZ[6]"/>
|
||||
<direct input="LC[7].FZ" name="SUPER_LOGIC_CELL-FZ[7]" output="SUPER_LOGIC_CELL.FZ[7]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<pb_type name="LOGIC_1">
|
||||
<output name="a" num_pins="1"/>
|
||||
<pb_type blif_model=".subckt logic_1" name="logic_1" num_pb="1">
|
||||
<output name="a" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="logic_1.a" name="LOGIC_1-a" output="LOGIC_1.a"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<pb_type name="LOGIC_0">
|
||||
<output name="a" num_pins="1"/>
|
||||
<pb_type blif_model=".subckt logic_0" name="gnd" num_pb="1">
|
||||
<output name="a" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct input="gnd.a" name="LOGIC_0-a" output="LOGIC_0.a"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
|
||||
|
|
@ -25,6 +25,9 @@ Feedback connections between LEs are implemented by the global routing architect
|
|||
Multi-mode Logic Element
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Physical Implementation
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
|
||||
|
||||
- a fracturable 4-input Look-Up Table (LUT)
|
||||
|
|
@ -40,9 +43,63 @@ As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
|
|||
|
||||
The LE can operate in different modes to map logic function efficiently
|
||||
|
||||
- 4-input LUT and single FF
|
||||
- Dual 3-input LUTs and 2 FFs
|
||||
- 2-bit shift registers
|
||||
- 4-input LUT and single FF (see details in :ref:`clb_arch_le_single_lut4_mode`).
|
||||
- Dual 3-input LUTs and 2 FFs (see details in :ref:`clb_arch_le_dual_lut3_mode`).
|
||||
- 2-bit shift registers (see details in :ref:`clb_arch_le_shift_reg_mode`).
|
||||
|
||||
|
||||
.. _clb_arch_le_single_lut4_mode:
|
||||
|
||||
Operating mode: LUT4 + FF
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements.
|
||||
As depicted in :numref:`fig_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic.
|
||||
|
||||
The operating mode is designed to efficiently implement 4-input functions.
|
||||
|
||||
.. _fig_fle_arch_single_lut4_mode:
|
||||
|
||||
.. figure:: ./figures/fle_arch_single_lut4_mode.svg
|
||||
:scale: 30%
|
||||
:alt: Logic element schematic
|
||||
|
||||
Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources).
|
||||
|
||||
.. _clb_arch_le_dual_lut3_mode:
|
||||
|
||||
Operating mode: Dual-LUT3
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements.
|
||||
As depicted in :numref:`fig_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs.
|
||||
|
||||
The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3.
|
||||
|
||||
.. _fig_fle_arch_dual_lut3_mode:
|
||||
|
||||
.. figure:: ./figures/fle_arch_dual_lut3_mode.svg
|
||||
:scale: 30%
|
||||
:alt: Logic element schematic
|
||||
|
||||
Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources).
|
||||
|
||||
.. _clb_arch_le_shift_reg_mode:
|
||||
|
||||
Operating mode: Shift-Register
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
As depicted in :numref:`fig_fle_arch_shift_reg_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers.
|
||||
|
||||
The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs.
|
||||
|
||||
.. _fig_fle_arch_shift_reg_mode:
|
||||
|
||||
.. figure:: ./figures/fle_arch_shift_reg_mode.svg
|
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:alt: Logic element schematic
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Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources).
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.. _clb_arch_scan_chain:
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<path d="M 503.02606 128.718 L 503.03084 177.75737 C 503.03084 177.75737 518.3379 170.3873 518.05446 170.10383 C 517.771 169.82036 517.7662 134.10383 517.7662 134.10383 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<g id="Graphic_107">
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<text transform="translate(504.64844 130.6322)" fill="white">
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
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</text>
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<g id="Graphic_106">
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<path d="M 504.8391 200.50512 L 504.8439 249.54448 C 504.8439 249.54448 520.151 242.1744 519.8675 241.89094 C 519.58404 241.60748 519.57926 205.89094 519.57926 205.89094 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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<g id="Graphic_105">
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<text transform="translate(506.4615 202.4193)" fill="white">
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="0" y="11">M</tspan>
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
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</text>
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</g>
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<g id="Graphic_104">
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<g id="Graphic_103">
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<text transform="translate(409.6394 217.59335)" fill="white">
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="25.509766">U</tspan>
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<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="white" x="1.3300781" y="40.01953">X</tspan>
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<g id="Graphic_101">
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<ellipse cx="464.18074" cy="201.95509" rx="2.58243758861832" ry="2.75000439423018" fill="black"/>
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<ellipse cx="464.18074" cy="201.95509" rx="2.58243758861832" ry="2.75000439423018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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</g>
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</svg>
|
||||
|
After Width: | Height: | Size: 21 KiB |
|
|
@ -59,6 +59,7 @@ write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench
|
|||
--print_top_testbench \
|
||||
--print_preconfig_top_testbench \
|
||||
--print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
|
||||
--include_signal_init \
|
||||
--explicit_port_mapping
|
||||
|
||||
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
|
|
|
|||
|
|
@ -6,20 +6,21 @@
|
|||
##################################
|
||||
# Define environment variables
|
||||
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
|
||||
set FPGA_NETLIST_HOME "../../FPGA1212_FC_HD_SKY_PNR/fpga_core";
|
||||
#set FPGA_NETLIST_HOME "../../FPGA1212_FC_HD_SKY_PNR/fpga_top";
|
||||
set FPGA_NETLIST_HOME "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top";
|
||||
set SDF_HOME "../../SDF"
|
||||
#
|
||||
# Enable reporting ALL the timing paths even those are NOT constrained
|
||||
set_app_var svr_enable_vpp true
|
||||
|
||||
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/skywater130_fd_sc_hd/db_nldm"
|
||||
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm"
|
||||
|
||||
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
|
||||
|
||||
# Top-level module name
|
||||
set DESIGN_NAME fpga_core;
|
||||
set DESIGN_NAME fpga_top;
|
||||
|
||||
set FPGA_NETLIST_FILES "fpga_core_icv_in_design.pt.v"
|
||||
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
|
||||
|
||||
##################################
|
||||
# Read timing libraries
|
||||
|
|
@ -30,15 +31,20 @@ read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nld
|
|||
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
|
||||
link_design ${DESIGN_NAME}
|
||||
|
||||
#########################################
|
||||
# Setup constraints to break combinational loops
|
||||
set_disable_timing [get_pins */*/*chan*]
|
||||
set_disable_timing [get_pins */*/*grid_pin*]
|
||||
|
||||
##################################
|
||||
# Read post-PnR parasitics
|
||||
read_parasitics ${FPGA_NETLIST_HOME}/fpga_core_icv_in_design.nominal_25.spef
|
||||
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
|
||||
|
||||
##################################
|
||||
# Write sdf file
|
||||
write_sdf -version 3.0 ${SDF_HOME}/FPGA1212_FC_HD_SKY_PNR/fpga_core_icv_in_design.pt.sdf
|
||||
write_sdf -version 3.0 ${SDF_HOME}/FPGA1212_FC_HD_SKY_PNR/fpga_top_icv_in_design.pt.sdf
|
||||
|
||||
##################################
|
||||
# Finish and quit
|
||||
# Comment it out if you want to debug
|
||||
#exit
|
||||
exit
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue