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4 Commits

Author SHA1 Message Date
Ganesh Gore 9f9897c5e2 [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
Ganesh Gore 0672f01e3a [Cleanup] Removed unused SDCs 2020-12-14 00:31:03 -07:00
Ganesh Gore 1a2e6de718 [SOFA_CHD] Removed large testbench file 2020-12-09 00:51:30 -07:00
Ganesh Gore 9284bbf8fa [SOFA_CHD] Added OpenFPGA taks and verilog netlist 2020-12-09 00:49:00 -07:00