Ganesh Gore
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452af85e98
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[Cleanup] Removed/Ignored testbench files from generated source
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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20dc203b31
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[FPGA1212_v1] Module level results
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2020-11-29 11:02:17 -07:00 |
Ganesh Gore
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225feaef3c
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[FPGA1212_v1] Added top-level pnr screenshots
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2020-11-29 10:59:15 -07:00 |
Ganesh Gore
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7db7c240e3
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[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed
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2020-11-29 10:24:03 -07:00 |
Ganesh Gore
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66d09da857
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[FPGA1212_v1] Updated the PostPnR Netlist and PnR Files
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2020-11-27 22:11:51 -07:00 |
Ganesh Gore
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ce4a6f72f5
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[FPGA1212_v1] Updated the task and PrePNR Verilog netlist
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2020-11-27 22:08:16 -07:00 |
Ganesh Gore
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c54cdcd3ef
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Added FPGA12x12 with CocoTB tests
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2020-11-21 16:07:09 -07:00 |