mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #67 from lnis-uofu/ganesh_dev
Updated CHD design with mux_primitive fix
This commit is contained in:
tangxifan
GitHub
commit
d6dc543870
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@ -1,68 +0,0 @@
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name: Caravel-QLSOFA_HD Deployment
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# = = = Env Variable = = = = =
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# secrets.TEST_REPO_KEY
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# secrets.QLSOFA_HD_KEY
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# secrets.SOFA_CHD_KEY
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# secrets.QLQLSOFA_HD_KEY
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# secrets.QLAP3_KEY
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# yq r -X deploy_sofa.yaml > ./workflows/deploy_sofa_hd.yaml
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env:
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SCAN_DIRECTORY: 'FPGA1212_RESET_HD_SKY_PNR/**'
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PROJ_SUFFIX: QLSOFA_HD
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DEST_DIR: Caravel-QLSOFA-HD
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DEST_REPO: lnis-uofu/Caravel-QLSOFA-HD
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REPO_KEY: ${{ secrets.QLSOFA_HD_KEY }}
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on:
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push:
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paths:
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- '.github/**'
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- 'SynRepoConfig/**'
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- '$SCAN_DIRECTORY'
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branches:
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- ganesh_dev
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pull_request:
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types: closed
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branches:
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- master
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jobs:
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linux:
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name: Updating release repository
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runs-on: ubuntu-latest
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steps:
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- name: Checkout SOFA-Chips
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uses: actions/checkout@v2
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with:
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path: SOFA-Chips
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- name: Checkout caravel repo
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uses: actions/checkout@master
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with:
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repository: lnis-uofu/Caravel-QLSOFA-HD
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path: Caravel-QLSOFA-HD
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- name: Checkout open_mpw_precheck repo
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uses: actions/checkout@master
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with:
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repository: efabless/open_mpw_precheck
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path: open_mpw_precheck
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- name: Perform checks with open_mpw_precheck
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uses: ganeshgore/docker-run-action@49cd3a1
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with:
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image: goreganesh/open_mpw_prechecker
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options: >
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-v ${{github.workspace}}/open_mpw_precheck:/usr/local/bin -v ${{github.workspace}}:/usr/local/workspace -e DEST_DIR=$DEST_DIR -e SCAN_DIRECTORY=$SCAN_DIRECTORY --workdir /usr/local/workspace
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run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
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- name: Deploy files
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# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
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- name: Deploy Changes
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uses: peaceiris/actions-gh-pages@v3
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# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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with:
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user_name: "lnis.uofu"
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user_email: "lnis.uofu@gmail.com"
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deploy_key: ${{ secrets.QLSOFA_HD_KEY }}
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external_repository: lnis-uofu/Caravel-QLSOFA-HD
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publish_dir: Caravel-QLSOFA-HD
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publish_branch: master
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disable_nojekyll: true
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commit_message: '[Deployment] ${{ github.event.head_commit.message }}'
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@ -1,68 +0,0 @@
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name: Caravel-SOFA_HD Deployment
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# = = = Env Variable = = = = =
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# secrets.TEST_REPO_KEY
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# secrets.SOFA_HD_KEY
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# secrets.SOFA_CHD_KEY
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# secrets.QLSOFA_HD_KEY
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# secrets.QLAP3_KEY
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# yq r -X deploy_sofa.yaml > ./workflows/deploy_sofa_hd.yaml
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env:
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SCAN_DIRECTORY: 'FPGA1212_FLAT_HD_SKY_PNR/**'
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PROJ_SUFFIX: SOFA_HD
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DEST_DIR: Caravel-SOFA-HD
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DEST_REPO: lnis-uofu/Caravel-SOFA-HD
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REPO_KEY: ${{ secrets.SOFA_HD_KEY }}
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||||
on:
|
||||
push:
|
||||
paths:
|
||||
- '.github/**'
|
||||
- 'SynRepoConfig/**'
|
||||
- '$SCAN_DIRECTORY'
|
||||
branches:
|
||||
- ganesh_dev
|
||||
pull_request:
|
||||
types: closed
|
||||
branches:
|
||||
- master
|
||||
jobs:
|
||||
linux:
|
||||
name: Updating release repository
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: Checkout SOFA-Chips
|
||||
uses: actions/checkout@v2
|
||||
with:
|
||||
path: SOFA-Chips
|
||||
- name: Checkout caravel repo
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uses: actions/checkout@master
|
||||
with:
|
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repository: lnis-uofu/Caravel-SOFA-HD
|
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path: Caravel-SOFA-HD
|
||||
- name: Checkout open_mpw_precheck repo
|
||||
uses: actions/checkout@master
|
||||
with:
|
||||
repository: efabless/open_mpw_precheck
|
||||
path: open_mpw_precheck
|
||||
- name: Perform checks with open_mpw_precheck
|
||||
uses: ganeshgore/docker-run-action@49cd3a1
|
||||
with:
|
||||
image: goreganesh/open_mpw_prechecker
|
||||
options: >
|
||||
-v ${{github.workspace}}/open_mpw_precheck:/usr/local/bin -v ${{github.workspace}}:/usr/local/workspace -e DEST_DIR=$DEST_DIR -e SCAN_DIRECTORY=$SCAN_DIRECTORY --workdir /usr/local/workspace
|
||||
|
||||
run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
|
||||
- name: Deploy files
|
||||
# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
|
||||
run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
|
||||
- name: Deploy Changes
|
||||
uses: peaceiris/actions-gh-pages@v3
|
||||
# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
|
||||
with:
|
||||
user_name: "lnis.uofu"
|
||||
user_email: "lnis.uofu@gmail.com"
|
||||
deploy_key: ${{ secrets.SOFA_HD_KEY }}
|
||||
external_repository: lnis-uofu/Caravel-SOFA-HD
|
||||
publish_dir: Caravel-SOFA-HD
|
||||
publish_branch: master
|
||||
disable_nojekyll: true
|
||||
commit_message: '[Deployment] ${{ github.event.head_commit.message }}'
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||||
|
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@ -6,5 +6,8 @@
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**/*_task/skywater
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**/*_Verilog/SRC_Skeleton
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**/*_Verilog/SRCBackup
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**/SRC/top_top_formal_verification.v
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**/DOC/build
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**/SRC**/*_tb.v
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**/SDC/**/*.sdc
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||||
!**/SDC/**/disable_configure_ports.sdc
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|
|
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@ -1,144 +0,0 @@
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#############################################
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# Synopsys Design Constraints (SDC)
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# For FPGA fabric
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# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
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# Author: Xifan TANG
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# Organization: University of Utah
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# Date: Sun Nov 29 02:09:07 2020
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#############################################
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#############################################
|
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# Define time unit
|
||||
#############################################
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set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
|
|
@ -1,208 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
|
|
@ -1,208 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.110371906e-09 -waveform {0 5.551859528e-10} [get_ports {clk[0]}]
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -1,322 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -1,182 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[23] -to fpga_top/cbx_1__1_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[23] -to fpga_top/cbx_1__1_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[20] -to fpga_top/cby_0__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[20] -to fpga_top/cby_0__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[21] -to fpga_top/cby_0__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[21] -to fpga_top/cby_0__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[22] -to fpga_top/cby_0__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[22] -to fpga_top/cby_0__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[23] -to fpga_top/cby_0__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[23] -to fpga_top/cby_0__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[25] -to fpga_top/cby_0__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[25] -to fpga_top/cby_0__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[26] -to fpga_top/cby_0__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[26] -to fpga_top/cby_0__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[27] -to fpga_top/cby_0__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[27] -to fpga_top/cby_0__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[28] -to fpga_top/cby_0__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[28] -to fpga_top/cby_0__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[29] -to fpga_top/cby_0__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[29] -to fpga_top/cby_0__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[23] -to fpga_top/cby_1__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[23] -to fpga_top/cby_1__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_lut*_*_in_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 8.319719358e-10 -waveform {0 4.159859679e-10} [get_ports {clk[0]}]
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_cin[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_cin[0] 1.599999994e-10
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[20] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[21] -to fpga_top/sb_0__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[22] -to fpga_top/sb_0__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[23] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[24] -to fpga_top/sb_0__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[25] -to fpga_top/sb_0__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[26] -to fpga_top/sb_0__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[27] -to fpga_top/sb_0__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[28] -to fpga_top/sb_0__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[29] -to fpga_top/sb_0__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[29] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[20] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[21] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[22] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[23] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[24] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[25] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[26] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[27] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[28] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
|
|
@ -1,123 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[28] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[27] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[26] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[25] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[24] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[23] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[22] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[21] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[20] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[29] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[28] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[27] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[26] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[25] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[24] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[23] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[22] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[21] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[20] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[29] -to fpga_top/sb_0__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
|
|
@ -1,217 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[21] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[25] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[29] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[29] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[25] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[21] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[29] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[28] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[27] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[26] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[25] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[24] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[23] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[22] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[21] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[20] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[29] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[28] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[27] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[26] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[25] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[24] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[23] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[22] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[21] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[20] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,155 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[20] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[21] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[22] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[23] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[24] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[25] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[26] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[27] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[28] -to fpga_top/sb_12__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[29] -to fpga_top/sb_12__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[29] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[20] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[21] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[22] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[23] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[24] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[25] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[26] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[27] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[28] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[21] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[25] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[29] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[29] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[25] -to fpga_top/sb_12__1_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[21] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[21] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[25] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[29] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[29] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[25] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[21] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,426 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -48,6 +48,7 @@ Untracked files:
|
|||
openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task
|
||||
openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task
|
||||
openfpga_flow/tasks/FPGA1212_RESET_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA1212_SOFA_CHD_task
|
||||
openfpga_flow/tasks/FPGA128128_FLAT_task
|
||||
|
|
|
|||
|
|
@ -1,182 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[23] -to fpga_top/cbx_1__1_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[23] -to fpga_top/cbx_1__1_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[20] -to fpga_top/cby_0__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[20] -to fpga_top/cby_0__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[21] -to fpga_top/cby_0__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[21] -to fpga_top/cby_0__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[22] -to fpga_top/cby_0__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[22] -to fpga_top/cby_0__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[23] -to fpga_top/cby_0__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[23] -to fpga_top/cby_0__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[25] -to fpga_top/cby_0__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[25] -to fpga_top/cby_0__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[26] -to fpga_top/cby_0__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[26] -to fpga_top/cby_0__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[27] -to fpga_top/cby_0__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[27] -to fpga_top/cby_0__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[28] -to fpga_top/cby_0__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[28] -to fpga_top/cby_0__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[29] -to fpga_top/cby_0__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[29] -to fpga_top/cby_0__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[23] -to fpga_top/cby_1__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[23] -to fpga_top/cby_1__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_lut*_*_in_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
# Description: Disable configuration outputs of all the programmable cells for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
# Date: Sun Dec 13 16:23:06 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram
|
||||
|
|
|
|||
|
|
@ -1,127 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 8.319719358e-10 -waveform {0 4.159859679e-10} [get_ports {clk[0]}]
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_cin[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_cin[0] 1.599999994e-10
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[20] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[21] -to fpga_top/sb_0__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[22] -to fpga_top/sb_0__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[23] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[24] -to fpga_top/sb_0__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[25] -to fpga_top/sb_0__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[26] -to fpga_top/sb_0__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[27] -to fpga_top/sb_0__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[28] -to fpga_top/sb_0__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[29] -to fpga_top/sb_0__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[29] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[20] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[21] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[22] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[23] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[24] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[25] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[26] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[27] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[28] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
|
|
@ -1,123 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[28] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[27] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[26] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[25] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[24] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[23] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[22] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[21] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[20] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[29] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[28] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[27] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[26] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[25] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[24] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[23] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[22] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[21] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[20] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[29] -to fpga_top/sb_0__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
|
|
@ -1,217 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[21] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[25] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[29] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[29] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[25] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[21] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[29] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[28] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[27] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[26] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[25] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[24] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[23] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[22] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[21] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[20] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[29] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[28] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[27] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[26] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[25] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[24] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[23] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[22] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[21] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[20] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,155 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[20] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[21] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[22] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[23] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[24] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[25] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[26] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[27] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[28] -to fpga_top/sb_12__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[29] -to fpga_top/sb_12__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[29] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[20] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[21] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[22] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[23] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[24] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[25] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[26] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[27] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[28] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[21] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[25] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[29] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[29] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[25] -to fpga_top/sb_12__1_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[21] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[21] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[25] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[29] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[29] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[25] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[21] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,426 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -36,6 +36,7 @@ output [0:0] out;
|
|||
//
|
||||
//
|
||||
|
||||
wire [0:0] out_inv;
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
|
|
@ -43,7 +44,11 @@ output [0:0] out;
|
|||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.Z(out[0])
|
||||
.Z(out_inv[0])
|
||||
);
|
||||
sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0(
|
||||
.A(out_inv[0]),
|
||||
.Y(out[0])
|
||||
);
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_1(
|
||||
.Q1(in[2]),
|
||||
|
|
@ -52,7 +57,11 @@ output [0:0] out;
|
|||
.S0B(mem_inv[2]),
|
||||
.S1(mem[3]),
|
||||
.S1B(mem_inv[3]),
|
||||
.Z(out[0])
|
||||
.Z(out_inv[0])
|
||||
);
|
||||
sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1(
|
||||
.A(out_inv[0]),
|
||||
.Y(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
|
@ -87,6 +96,7 @@ output [0:0] out;
|
|||
//
|
||||
//
|
||||
|
||||
wire [0:0] out_inv;
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
|
|
@ -94,7 +104,11 @@ output [0:0] out;
|
|||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.Z(out[0])
|
||||
.Z(out_inv[0])
|
||||
);
|
||||
sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0(
|
||||
.A(out_inv[0]),
|
||||
.Y(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
|
@ -129,6 +143,7 @@ output [0:0] out;
|
|||
//
|
||||
//
|
||||
|
||||
wire [0:0] out_inv;
|
||||
scs8hd_muxinv3_1 scs8hd_muxinv3_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
|
|
@ -139,7 +154,11 @@ output [0:0] out;
|
|||
.S1B(mem_inv[1]),
|
||||
.S2(mem[2]),
|
||||
.S2B(mem_inv[2]),
|
||||
.Z(out[0])
|
||||
.Z(out_inv[0])
|
||||
);
|
||||
sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0(
|
||||
.A(out_inv[0]),
|
||||
.Y(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
|
@ -174,6 +193,7 @@ output [0:0] out;
|
|||
//
|
||||
//
|
||||
|
||||
wire [0:0] out_inv;
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
|
|
@ -181,7 +201,11 @@ output [0:0] out;
|
|||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.Z(out[0])
|
||||
.Z(out_inv[0])
|
||||
);
|
||||
sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0(
|
||||
.A(out_inv[0]),
|
||||
.Y(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
|
@ -216,6 +240,7 @@ output [0:0] out;
|
|||
//
|
||||
//
|
||||
|
||||
wire [0:0] out_inv;
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
|
|
@ -223,7 +248,11 @@ output [0:0] out;
|
|||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.Z(out[0])
|
||||
.Z(out_inv[0])
|
||||
);
|
||||
sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0(
|
||||
.A(out_inv[0]),
|
||||
.Y(out[0])
|
||||
);
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_1(
|
||||
.Q1(in[2]),
|
||||
|
|
@ -232,7 +261,11 @@ output [0:0] out;
|
|||
.S0B(mem_inv[2]),
|
||||
.S1(mem[3]),
|
||||
.S1B(mem_inv[3]),
|
||||
.Z(out[0])
|
||||
.Z(out_inv[0])
|
||||
);
|
||||
sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1(
|
||||
.A(out_inv[0]),
|
||||
.Y(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
|
@ -267,6 +300,7 @@ output [0:0] out;
|
|||
//
|
||||
//
|
||||
|
||||
wire [0:0] out_inv;
|
||||
sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0(
|
||||
.A1(in[0]),
|
||||
.A0(in[1]),
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
- Fabric bitstream
|
||||
- Author: Xifan TANG
|
||||
- Organization: University of Utah
|
||||
- Date: Tue Dec 8 15:34:09 2020
|
||||
- Date: Sun Dec 13 16:23:01 2020
|
||||
-->
|
||||
|
||||
<fabric_bitstream>
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
- Architecture independent bitstream
|
||||
- Author: Xifan TANG
|
||||
- Organization: University of Utah
|
||||
- Date: Tue Dec 8 15:34:08 2020
|
||||
- Date: Sun Dec 13 16:23:00 2020
|
||||
-->
|
||||
|
||||
<bitstream_block name="fpga_top" hierarchy_level="0">
|
||||
|
|
|
|||
|
|
@ -281,12 +281,12 @@ Device Utilization: 0.02 (target 1.00)
|
|||
|
||||
Netlist conversion complete.
|
||||
|
||||
# Packing took 0.03 seconds (max_rss 10.7 MiB, delta_rss +0.7 MiB)
|
||||
# Packing took 0.01 seconds (max_rss 10.7 MiB, delta_rss +0.7 MiB)
|
||||
# Load Packing
|
||||
Begin loading packed FPGA netlist file.
|
||||
Netlist generated from file 'top.net'.
|
||||
Detected 0 constant generators (to see names run with higher pack verbosity)
|
||||
Finished loading packed FPGA netlist file (took 0.02 seconds).
|
||||
Finished loading packed FPGA netlist file (took 0 seconds).
|
||||
Warning 65: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
|
||||
# Load Packing took 0.01 seconds (max_rss 10.7 MiB, delta_rss +0.1 MiB)
|
||||
Warning 66: Netlist contains 0 global net to non-global architecture pin connections
|
||||
|
|
@ -374,10 +374,10 @@ Warning 105: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53
|
|||
Warning 106: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
|
||||
Warning 107: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin.
|
||||
This is possible on a fringe node based on low Fc_out, N, and certain lengths.
|
||||
## Build tileable routing resource graph took 0.19 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
|
||||
## Build tileable routing resource graph took 0.29 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
|
||||
RR Graph Nodes: 23404
|
||||
RR Graph Edges: 121880
|
||||
# Create Device took 0.19 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
|
||||
# Create Device took 0.29 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
|
||||
|
||||
# Placement
|
||||
## Computing placement delta delay look-up
|
||||
|
|
@ -418,12 +418,12 @@ Warning 140: in check_rr_node: RR node: 13066 type: OPIN location: (11,1) pin: 5
|
|||
Warning 141: in check_rr_node: RR node: 14352 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||||
Warning 142: in check_rr_node: RR node: 14353 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
Warning 143: in check_rr_node: RR node: 14354 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
|
||||
### Build routing resource graph took 0.08 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
|
||||
### Build routing resource graph took 0.10 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
|
||||
RR Graph Nodes: 23120
|
||||
RR Graph Edges: 105560
|
||||
### Computing delta delays
|
||||
### Computing delta delays took 0.03 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB)
|
||||
## Computing placement delta delay look-up took 0.11 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
|
||||
### Computing delta delays took 0.04 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB)
|
||||
## Computing placement delta delay look-up took 0.15 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
|
||||
|
||||
There are 3 point to point connections in this circuit.
|
||||
|
||||
|
|
@ -526,7 +526,7 @@ Placement total # of swap attempts: 232
|
|||
Swaps aborted : 0 ( 0.0 %)
|
||||
|
||||
Aborted Move Reasons:
|
||||
# Placement took 0.11 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB)
|
||||
# Placement took 0.15 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB)
|
||||
|
||||
# Routing
|
||||
## Build tileable routing resource graph
|
||||
|
|
@ -570,7 +570,7 @@ Warning 178: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53
|
|||
Warning 179: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
|
||||
Warning 180: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin.
|
||||
This is possible on a fringe node based on low Fc_out, N, and certain lengths.
|
||||
## Build tileable routing resource graph took 0.14 seconds (max_rss 21.5 MiB, delta_rss +0.3 MiB)
|
||||
## Build tileable routing resource graph took 0.19 seconds (max_rss 21.5 MiB, delta_rss +0.3 MiB)
|
||||
RR Graph Nodes: 23404
|
||||
RR Graph Edges: 121880
|
||||
Confirming router algorithm: TIMING_DRIVEN.
|
||||
|
|
@ -583,7 +583,7 @@ Restoring best routing
|
|||
Critical path: 0.69331 ns
|
||||
Successfully routed after 1 routing iterations.
|
||||
Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 124 total_heap_pops: 52
|
||||
# Routing took 0.15 seconds (max_rss 22.3 MiB, delta_rss +1.1 MiB)
|
||||
# Routing took 0.20 seconds (max_rss 22.3 MiB, delta_rss +1.1 MiB)
|
||||
|
||||
Checking to ensure routing is legal...
|
||||
Completed routing consistency check successfully.
|
||||
|
|
@ -701,9 +701,9 @@ Setup slack histogram:
|
|||
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||||
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||||
|
||||
Timing analysis took 0.000266012 seconds (0.000240965 STA, 2.5047e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined).
|
||||
Timing analysis took 0.000354561 seconds (0.000323356 STA, 3.1205e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined).
|
||||
VPR suceeded
|
||||
The entire flow of VPR took 0.53 seconds (max_rss 22.5 MiB)
|
||||
The entire flow of VPR took 0.72 seconds (max_rss 22.5 MiB)
|
||||
|
||||
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
|
||||
|
||||
|
|
@ -935,7 +935,7 @@ Annotating previous nodes for rr_node...Done with 15 nodes mapping
|
|||
[99%] Backannotated GSB[12][11]
|
||||
[100%] Backannotated GSB[12][12]
|
||||
Backannotated 169 General Switch Blocks (GSBs).
|
||||
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 22.8 MiB, delta_rss +0.0 MiB)
|
||||
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.01 seconds (max_rss 22.8 MiB, delta_rss +0.0 MiB)
|
||||
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
|
||||
[0%] Sorted edges for GSB[0][0]
|
||||
[1%] Sorted edges for GSB[0][1]
|
||||
|
|
@ -1107,7 +1107,7 @@ Backannotated 169 General Switch Blocks (GSBs).
|
|||
[99%] Sorted edges for GSB[12][11]
|
||||
[100%] Sorted edges for GSB[12][12]
|
||||
Sorted edges for 169 General Switch Blocks (GSBs).
|
||||
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.07 seconds (max_rss 23.3 MiB, delta_rss +0.5 MiB)
|
||||
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.09 seconds (max_rss 23.3 MiB, delta_rss +0.5 MiB)
|
||||
# Build a library of physical multiplexers
|
||||
Built a multiplexer library of 16 physical multiplexers.
|
||||
Maximum multiplexer size is 16.
|
||||
|
|
@ -1124,7 +1124,7 @@ Average net density: 0.42
|
|||
Median net density: 0.00
|
||||
Average net density after weighting: 0.42
|
||||
Will apply 2 operating clock cycles to simulations
|
||||
Link OpenFPGA architecture to VPR architecture took 0.08 seconds (max_rss 23.6 MiB, delta_rss +0.8 MiB)
|
||||
Link OpenFPGA architecture to VPR architecture took 0.10 seconds (max_rss 23.6 MiB, delta_rss +0.8 MiB)
|
||||
|
||||
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_SOFA_CHD_task/arch/fabric_key.xml
|
||||
|
||||
|
|
@ -1138,7 +1138,7 @@ Confirm selected options when call command 'build_fabric':
|
|||
--verbose: off
|
||||
Identify unique General Switch Blocks (GSBs)
|
||||
Detected 9 unique general switch blocks from a total of 169 (compression rate=1777.78%)
|
||||
Identify unique General Switch Blocks (GSBs) took 0.12 seconds (max_rss 23.6 MiB, delta_rss +0.0 MiB)
|
||||
Identify unique General Switch Blocks (GSBs) took 0.16 seconds (max_rss 23.6 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Read Fabric Key
|
||||
Read Fabric Key took 0.00 seconds (max_rss 23.7 MiB, delta_rss +0.1 MiB)
|
||||
|
|
@ -1180,9 +1180,9 @@ Building physical tiles...Done
|
|||
## Add module nets for inter-tile connections
|
||||
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 53.1 MiB, delta_rss +0.5 MiB)
|
||||
## Add module nets for configuration buses
|
||||
## Add module nets for configuration buses took 0.03 seconds (max_rss 55.1 MiB, delta_rss +1.5 MiB)
|
||||
# Build FPGA fabric module took 0.19 seconds (max_rss 55.1 MiB, delta_rss +27.1 MiB)
|
||||
Build fabric module graph took 0.21 seconds (max_rss 55.1 MiB, delta_rss +31.4 MiB)
|
||||
## Add module nets for configuration buses took 0.01 seconds (max_rss 55.1 MiB, delta_rss +1.5 MiB)
|
||||
# Build FPGA fabric module took 0.17 seconds (max_rss 55.1 MiB, delta_rss +27.1 MiB)
|
||||
Build fabric module graph took 0.19 seconds (max_rss 55.1 MiB, delta_rss +31.4 MiB)
|
||||
Create I/O location mapping for top module
|
||||
Create I/O location mapping for top module took 0.00 seconds (max_rss 55.1 MiB, delta_rss +0.0 MiB)
|
||||
Create global port info for top module
|
||||
|
|
@ -1217,10 +1217,10 @@ Generating bitstream for X-direction Connection blocks ...Done
|
|||
Generating bitstream for Y-direction Connection blocks ...Done
|
||||
|
||||
Build fabric-independent bitstream for implementation 'top'
|
||||
took 0.26 seconds (max_rss 60.4 MiB, delta_rss +5.2 MiB)
|
||||
took 0.15 seconds (max_rss 60.4 MiB, delta_rss +5.2 MiB)
|
||||
Warning 185: Directory path is empty and nothing will be created.
|
||||
Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
|
||||
Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.73 seconds (max_rss 60.4 MiB, delta_rss +0.0 MiB)
|
||||
Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.60 seconds (max_rss 60.4 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: build_fabric_bitstream
|
||||
|
||||
|
|
@ -1231,7 +1231,7 @@ Build fabric dependent bitstream
|
|||
|
||||
|
||||
Build fabric dependent bitstream
|
||||
took 0.09 seconds (max_rss 65.5 MiB, delta_rss +5.2 MiB)
|
||||
took 0.04 seconds (max_rss 65.5 MiB, delta_rss +5.2 MiB)
|
||||
|
||||
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
|
||||
|
||||
|
|
@ -1251,7 +1251,7 @@ Confirm selected options when call command 'write_fabric_bitstream':
|
|||
--verbose: off
|
||||
Warning 187: Directory path is empty and nothing will be created.
|
||||
Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml'
|
||||
Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.16 seconds (max_rss 65.5 MiB, delta_rss +0.0 MiB)
|
||||
Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.14 seconds (max_rss 65.5 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose
|
||||
|
||||
|
|
@ -1314,7 +1314,7 @@ Building physical tiles...Done
|
|||
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
|
||||
Written 92 Verilog modules in total
|
||||
Write Verilog netlists for FPGA fabric
|
||||
took 0.64 seconds (max_rss 68.4 MiB, delta_rss +2.8 MiB)
|
||||
took 0.45 seconds (max_rss 68.4 MiB, delta_rss +2.8 MiB)
|
||||
|
||||
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
|
||||
|
||||
|
|
@ -1336,17 +1336,17 @@ Write Verilog testbenches for FPGA fabric
|
|||
|
||||
Warning 189: Directory './SRC' already exists. Will overwrite contents
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 3.54 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB)
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 3.67 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB)
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB)
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
|
||||
Will use 81453 configuration clock cycles to top testbench
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.21 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB)
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.23 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB)
|
||||
Succeed to create directory './SimulationDeck'
|
||||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
|
||||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 68.5 MiB, delta_rss +0.0 MiB)
|
||||
Write Verilog testbenches for FPGA fabric
|
||||
took 3.77 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB)
|
||||
took 3.93 seconds (max_rss 68.5 MiB, delta_rss +0.2 MiB)
|
||||
|
||||
Command line to execute: write_pnr_sdc --file ./SDC
|
||||
|
||||
|
|
@ -1370,17 +1370,17 @@ Succeed to create directory './SDC'
|
|||
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc'
|
||||
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 68.5 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc'
|
||||
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.1 MiB)
|
||||
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc'
|
||||
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.07 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.05 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc'
|
||||
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constrain Switch Block timing for P&R flow
|
||||
Write SDC for constrain Switch Block timing for P&R flow took 0.04 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constrain Connection Block timing for P&R flow
|
||||
Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constrain Connection Block timing for P&R flow took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constraining grid timing for P&R flow
|
||||
Write SDC for constraining grid timing for P&R flow took 0.02 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constraining grid timing for P&R flow took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
|
||||
|
|
@ -1390,7 +1390,7 @@ Confirm selected options when call command 'write_sdc_disable_timing_configure_p
|
|||
--verbose: off
|
||||
Warning 190: Directory './SDC' already exists. Will overwrite contents
|
||||
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc'
|
||||
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.10 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.11 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
|
|
@ -1401,7 +1401,7 @@ Confirm selected options when call command 'write_analysis_sdc':
|
|||
--time_unit: off
|
||||
Succeed to create directory './SDC_analysis'
|
||||
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc'
|
||||
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 0.97 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 1.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: exit
|
||||
|
||||
|
|
@ -1409,6 +1409,6 @@ Confirm selected options when call command 'exit':
|
|||
|
||||
Finish execution with 0 errors
|
||||
|
||||
The entire OpenFPGA flow took 7.48 seconds
|
||||
The entire OpenFPGA flow took 7.3 seconds
|
||||
|
||||
Thank you for using OpenFPGA!
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
## FPGA1212_SOFA_CHD_PNR
|
||||
|
||||
https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,647 @@
|
|||
Found test fpga_reset_hd_sky_pnr.ConfigChainTestFull
|
||||
Running test 1/1: ConfigChainTestFull
|
||||
Starting test: "ConfigChainTestFull"
|
||||
Description: None
|
||||
Signal received at sb_12__12_ at 65
|
||||
Signal received at cbx_12__12_ at 35
|
||||
Signal received at sb_11__12_ at 81
|
||||
Signal received at cbx_11__12_ at 35
|
||||
Signal received at sb_10__12_ at 81
|
||||
Signal received at cbx_10__12_ at 35
|
||||
Signal received at sb_9__12_ at 81
|
||||
Signal received at cbx_9__12_ at 35
|
||||
Signal received at sb_8__12_ at 81
|
||||
Signal received at cbx_8__12_ at 35
|
||||
Signal received at sb_7__12_ at 81
|
||||
Signal received at cbx_7__12_ at 35
|
||||
Signal received at sb_6__12_ at 81
|
||||
Signal received at cbx_6__12_ at 35
|
||||
Signal received at sb_5__12_ at 81
|
||||
Signal received at cbx_5__12_ at 35
|
||||
Signal received at sb_4__12_ at 81
|
||||
Signal received at cbx_4__12_ at 35
|
||||
Signal received at sb_3__12_ at 81
|
||||
Signal received at cbx_3__12_ at 35
|
||||
Signal received at sb_2__12_ at 81
|
||||
Signal received at cbx_2__12_ at 35
|
||||
Signal received at sb_1__12_ at 81
|
||||
Signal received at cbx_1__12_ at 35
|
||||
Signal received at sb_0__12_ at 41
|
||||
Signal received at cby_0__12_ at 3
|
||||
Signal received at grid_clb_1__12_ at 116
|
||||
Signal received at cby_1__12_ at 32
|
||||
Signal received at grid_clb_2__12_ at 116
|
||||
Signal received at cby_2__12_ at 32
|
||||
Signal received at grid_clb_3__12_ at 116
|
||||
Signal received at cby_3__12_ at 32
|
||||
Signal received at grid_clb_4__12_ at 116
|
||||
Signal received at cby_4__12_ at 32
|
||||
Signal received at grid_clb_5__12_ at 116
|
||||
Signal received at cby_5__12_ at 32
|
||||
Signal received at grid_clb_6__12_ at 116
|
||||
Signal received at cby_6__12_ at 32
|
||||
Signal received at grid_clb_7__12_ at 116
|
||||
Signal received at cby_7__12_ at 32
|
||||
Signal received at grid_clb_8__12_ at 116
|
||||
Signal received at cby_8__12_ at 32
|
||||
Signal received at grid_clb_9__12_ at 116
|
||||
Signal received at cby_9__12_ at 32
|
||||
Signal received at grid_clb_10__12_ at 116
|
||||
Signal received at cby_10__12_ at 32
|
||||
Signal received at grid_clb_11__12_ at 116
|
||||
Signal received at cby_11__12_ at 32
|
||||
Signal received at grid_clb_12__12_ at 116
|
||||
Signal received at cby_12__12_ at 35
|
||||
Signal received at sb_12__11_ at 83
|
||||
Signal received at cbx_12__11_ at 33
|
||||
Signal received at sb_11__11_ at 88
|
||||
Signal received at cbx_11__11_ at 32
|
||||
Signal received at sb_10__11_ at 88
|
||||
Signal received at cbx_10__11_ at 32
|
||||
Signal received at sb_9__11_ at 88
|
||||
Signal received at cbx_9__11_ at 32
|
||||
Signal received at sb_8__11_ at 88
|
||||
Signal received at cbx_8__11_ at 32
|
||||
Signal received at sb_7__11_ at 88
|
||||
Signal received at cbx_7__11_ at 32
|
||||
Signal received at sb_6__11_ at 88
|
||||
Signal received at cbx_6__11_ at 32
|
||||
Signal received at sb_5__11_ at 88
|
||||
Signal received at cbx_5__11_ at 32
|
||||
Signal received at sb_4__11_ at 88
|
||||
Signal received at cbx_4__11_ at 32
|
||||
Signal received at sb_3__11_ at 88
|
||||
Signal received at cbx_3__11_ at 32
|
||||
Signal received at sb_2__11_ at 88
|
||||
Signal received at cbx_2__11_ at 32
|
||||
Signal received at sb_1__11_ at 88
|
||||
Signal received at cbx_1__11_ at 32
|
||||
Signal received at sb_0__11_ at 82
|
||||
Signal received at cby_0__11_ at 3
|
||||
Signal received at grid_clb_1__11_ at 116
|
||||
Signal received at cby_1__11_ at 32
|
||||
Signal received at grid_clb_2__11_ at 116
|
||||
Signal received at cby_2__11_ at 32
|
||||
Signal received at grid_clb_3__11_ at 116
|
||||
Signal received at cby_3__11_ at 32
|
||||
Signal received at grid_clb_4__11_ at 116
|
||||
Signal received at cby_4__11_ at 32
|
||||
Signal received at grid_clb_5__11_ at 116
|
||||
Signal received at cby_5__11_ at 32
|
||||
Signal received at grid_clb_6__11_ at 116
|
||||
Signal received at cby_6__11_ at 32
|
||||
Signal received at grid_clb_7__11_ at 116
|
||||
Signal received at cby_7__11_ at 32
|
||||
Signal received at grid_clb_8__11_ at 116
|
||||
Signal received at cby_8__11_ at 32
|
||||
Signal received at grid_clb_9__11_ at 116
|
||||
Signal received at cby_9__11_ at 32
|
||||
Signal received at grid_clb_10__11_ at 116
|
||||
Signal received at cby_10__11_ at 32
|
||||
Signal received at grid_clb_11__11_ at 116
|
||||
Signal received at cby_11__11_ at 32
|
||||
Signal received at grid_clb_12__11_ at 116
|
||||
Signal received at cby_12__11_ at 35
|
||||
Signal received at sb_12__10_ at 83
|
||||
Signal received at cbx_12__10_ at 32
|
||||
Signal received at sb_11__10_ at 88
|
||||
Signal received at cbx_11__10_ at 32
|
||||
Signal received at sb_10__10_ at 88
|
||||
Signal received at cbx_10__10_ at 32
|
||||
Signal received at sb_9__10_ at 88
|
||||
Signal received at cbx_9__10_ at 32
|
||||
Signal received at sb_8__10_ at 88
|
||||
Signal received at cbx_8__10_ at 32
|
||||
Signal received at sb_7__10_ at 88
|
||||
Signal received at cbx_7__10_ at 32
|
||||
Signal received at sb_6__10_ at 88
|
||||
Signal received at cbx_6__10_ at 32
|
||||
Signal received at sb_5__10_ at 88
|
||||
Signal received at cbx_5__10_ at 32
|
||||
Signal received at sb_4__10_ at 88
|
||||
Signal received at cbx_4__10_ at 32
|
||||
Signal received at sb_3__10_ at 88
|
||||
Signal received at cbx_3__10_ at 32
|
||||
Signal received at sb_2__10_ at 88
|
||||
Signal received at cbx_2__10_ at 32
|
||||
Signal received at sb_1__10_ at 88
|
||||
Signal received at cbx_1__10_ at 32
|
||||
Signal received at sb_0__10_ at 82
|
||||
Signal received at cby_0__10_ at 3
|
||||
Signal received at grid_clb_1__10_ at 116
|
||||
Signal received at cby_1__10_ at 32
|
||||
Signal received at grid_clb_2__10_ at 116
|
||||
Signal received at cby_2__10_ at 32
|
||||
Signal received at grid_clb_3__10_ at 116
|
||||
Signal received at cby_3__10_ at 32
|
||||
Signal received at grid_clb_4__10_ at 116
|
||||
Signal received at cby_4__10_ at 32
|
||||
Signal received at grid_clb_5__10_ at 116
|
||||
Signal received at cby_5__10_ at 32
|
||||
Signal received at grid_clb_6__10_ at 116
|
||||
Signal received at cby_6__10_ at 32
|
||||
Signal received at grid_clb_7__10_ at 116
|
||||
Signal received at cby_7__10_ at 32
|
||||
Signal received at grid_clb_8__10_ at 116
|
||||
Signal received at cby_8__10_ at 32
|
||||
Signal received at grid_clb_9__10_ at 116
|
||||
Signal received at cby_9__10_ at 32
|
||||
Signal received at grid_clb_10__10_ at 116
|
||||
Signal received at cby_10__10_ at 32
|
||||
Signal received at grid_clb_11__10_ at 116
|
||||
Signal received at cby_11__10_ at 32
|
||||
Signal received at grid_clb_12__10_ at 116
|
||||
Signal received at cby_12__10_ at 35
|
||||
Signal received at sb_12__9_ at 83
|
||||
Signal received at cbx_12__9_ at 32
|
||||
Signal received at sb_11__9_ at 88
|
||||
Signal received at cbx_11__9_ at 32
|
||||
Signal received at sb_10__9_ at 88
|
||||
Signal received at cbx_10__9_ at 32
|
||||
Signal received at sb_9__9_ at 88
|
||||
Signal received at cbx_9__9_ at 32
|
||||
Signal received at sb_8__9_ at 88
|
||||
Signal received at cbx_8__9_ at 32
|
||||
Signal received at sb_7__9_ at 88
|
||||
Signal received at cbx_7__9_ at 32
|
||||
Signal received at sb_6__9_ at 88
|
||||
Signal received at cbx_6__9_ at 32
|
||||
Signal received at sb_5__9_ at 88
|
||||
Signal received at cbx_5__9_ at 32
|
||||
Signal received at sb_4__9_ at 88
|
||||
Signal received at cbx_4__9_ at 32
|
||||
Signal received at sb_3__9_ at 88
|
||||
Signal received at cbx_3__9_ at 32
|
||||
Signal received at sb_2__9_ at 88
|
||||
Signal received at cbx_2__9_ at 32
|
||||
Signal received at sb_1__9_ at 88
|
||||
Signal received at cbx_1__9_ at 32
|
||||
Signal received at sb_0__9_ at 82
|
||||
Signal received at cby_0__9_ at 3
|
||||
Signal received at grid_clb_1__9_ at 116
|
||||
Signal received at cby_1__9_ at 32
|
||||
Signal received at grid_clb_2__9_ at 116
|
||||
Signal received at cby_2__9_ at 32
|
||||
Signal received at grid_clb_3__9_ at 116
|
||||
Signal received at cby_3__9_ at 32
|
||||
Signal received at grid_clb_4__9_ at 116
|
||||
Signal received at cby_4__9_ at 32
|
||||
Signal received at grid_clb_5__9_ at 116
|
||||
Signal received at cby_5__9_ at 32
|
||||
Signal received at grid_clb_6__9_ at 116
|
||||
Signal received at cby_6__9_ at 32
|
||||
Signal received at grid_clb_7__9_ at 116
|
||||
Signal received at cby_7__9_ at 32
|
||||
Signal received at grid_clb_8__9_ at 116
|
||||
Signal received at cby_8__9_ at 32
|
||||
Signal received at grid_clb_9__9_ at 116
|
||||
Signal received at cby_9__9_ at 32
|
||||
Signal received at grid_clb_10__9_ at 116
|
||||
Signal received at cby_10__9_ at 32
|
||||
Signal received at grid_clb_11__9_ at 116
|
||||
Signal received at cby_11__9_ at 32
|
||||
Signal received at grid_clb_12__9_ at 116
|
||||
Signal received at cby_12__9_ at 35
|
||||
Signal received at sb_12__8_ at 84
|
||||
Signal received at cbx_12__8_ at 32
|
||||
Signal received at sb_11__8_ at 88
|
||||
Signal received at cbx_11__8_ at 32
|
||||
Signal received at sb_10__8_ at 88
|
||||
Signal received at cbx_10__8_ at 32
|
||||
Signal received at sb_9__8_ at 88
|
||||
Signal received at cbx_9__8_ at 32
|
||||
Signal received at sb_8__8_ at 88
|
||||
Signal received at cbx_8__8_ at 32
|
||||
Signal received at sb_7__8_ at 88
|
||||
Signal received at cbx_7__8_ at 32
|
||||
Signal received at sb_6__8_ at 88
|
||||
Signal received at cbx_6__8_ at 32
|
||||
Signal received at sb_5__8_ at 88
|
||||
Signal received at cbx_5__8_ at 32
|
||||
Signal received at sb_4__8_ at 88
|
||||
Signal received at cbx_4__8_ at 32
|
||||
Signal received at sb_3__8_ at 88
|
||||
Signal received at cbx_3__8_ at 32
|
||||
Signal received at sb_2__8_ at 88
|
||||
Signal received at cbx_2__8_ at 32
|
||||
Signal received at sb_1__8_ at 88
|
||||
Signal received at cbx_1__8_ at 32
|
||||
Signal received at sb_0__8_ at 82
|
||||
Signal received at cby_0__8_ at 3
|
||||
Signal received at grid_clb_1__8_ at 116
|
||||
Signal received at cby_1__8_ at 32
|
||||
Signal received at grid_clb_2__8_ at 116
|
||||
Signal received at cby_2__8_ at 32
|
||||
Signal received at grid_clb_3__8_ at 116
|
||||
Signal received at cby_3__8_ at 32
|
||||
Signal received at grid_clb_4__8_ at 116
|
||||
Signal received at cby_4__8_ at 32
|
||||
Signal received at grid_clb_5__8_ at 116
|
||||
Signal received at cby_5__8_ at 32
|
||||
Signal received at grid_clb_6__8_ at 116
|
||||
Signal received at cby_6__8_ at 32
|
||||
Signal received at grid_clb_7__8_ at 116
|
||||
Signal received at cby_7__8_ at 32
|
||||
Signal received at grid_clb_8__8_ at 116
|
||||
Signal received at cby_8__8_ at 32
|
||||
Signal received at grid_clb_9__8_ at 116
|
||||
Signal received at cby_9__8_ at 32
|
||||
Signal received at grid_clb_10__8_ at 116
|
||||
Signal received at cby_10__8_ at 32
|
||||
Signal received at grid_clb_11__8_ at 116
|
||||
Signal received at cby_11__8_ at 32
|
||||
Signal received at grid_clb_12__8_ at 116
|
||||
Signal received at cby_12__8_ at 35
|
||||
Signal received at sb_12__7_ at 83
|
||||
Signal received at cbx_12__7_ at 32
|
||||
Signal received at sb_11__7_ at 88
|
||||
Signal received at cbx_11__7_ at 32
|
||||
Signal received at sb_10__7_ at 88
|
||||
Signal received at cbx_10__7_ at 32
|
||||
Signal received at sb_9__7_ at 88
|
||||
Signal received at cbx_9__7_ at 32
|
||||
Signal received at sb_8__7_ at 88
|
||||
Signal received at cbx_8__7_ at 32
|
||||
Signal received at sb_7__7_ at 88
|
||||
Signal received at cbx_7__7_ at 32
|
||||
Signal received at sb_6__7_ at 88
|
||||
Signal received at cbx_6__7_ at 32
|
||||
Signal received at sb_5__7_ at 88
|
||||
Signal received at cbx_5__7_ at 32
|
||||
Signal received at sb_4__7_ at 88
|
||||
Signal received at cbx_4__7_ at 32
|
||||
Signal received at sb_3__7_ at 88
|
||||
Signal received at cbx_3__7_ at 32
|
||||
Signal received at sb_2__7_ at 88
|
||||
Signal received at cbx_2__7_ at 32
|
||||
Signal received at sb_1__7_ at 88
|
||||
Signal received at cbx_1__7_ at 32
|
||||
Signal received at sb_0__7_ at 82
|
||||
Signal received at cby_0__7_ at 3
|
||||
Signal received at grid_clb_1__7_ at 116
|
||||
Signal received at cby_1__7_ at 32
|
||||
Signal received at grid_clb_2__7_ at 116
|
||||
Signal received at cby_2__7_ at 32
|
||||
Signal received at grid_clb_3__7_ at 116
|
||||
Signal received at cby_3__7_ at 32
|
||||
Signal received at grid_clb_4__7_ at 116
|
||||
Signal received at cby_4__7_ at 32
|
||||
Signal received at grid_clb_5__7_ at 116
|
||||
Signal received at cby_5__7_ at 32
|
||||
Signal received at grid_clb_6__7_ at 116
|
||||
Signal received at cby_6__7_ at 32
|
||||
Signal received at grid_clb_7__7_ at 116
|
||||
Signal received at cby_7__7_ at 32
|
||||
Signal received at grid_clb_8__7_ at 116
|
||||
Signal received at cby_8__7_ at 32
|
||||
Signal received at grid_clb_9__7_ at 116
|
||||
Signal received at cby_9__7_ at 32
|
||||
Signal received at grid_clb_10__7_ at 116
|
||||
Signal received at cby_10__7_ at 32
|
||||
Signal received at grid_clb_11__7_ at 116
|
||||
Signal received at cby_11__7_ at 32
|
||||
Signal received at grid_clb_12__7_ at 116
|
||||
Signal received at cby_12__7_ at 35
|
||||
Signal received at sb_12__6_ at 83
|
||||
Signal received at cbx_12__6_ at 32
|
||||
Signal received at sb_11__6_ at 88
|
||||
Signal received at cbx_11__6_ at 32
|
||||
Signal received at sb_10__6_ at 88
|
||||
Signal received at cbx_10__6_ at 32
|
||||
Signal received at sb_9__6_ at 88
|
||||
Signal received at cbx_9__6_ at 32
|
||||
Signal received at sb_8__6_ at 88
|
||||
Signal received at cbx_8__6_ at 32
|
||||
Signal received at sb_7__6_ at 88
|
||||
Signal received at cbx_7__6_ at 32
|
||||
Signal received at sb_6__6_ at 88
|
||||
Signal received at cbx_6__6_ at 32
|
||||
Signal received at sb_5__6_ at 88
|
||||
Signal received at cbx_5__6_ at 32
|
||||
Signal received at sb_4__6_ at 88
|
||||
Signal received at cbx_4__6_ at 32
|
||||
Signal received at sb_3__6_ at 88
|
||||
Signal received at cbx_3__6_ at 32
|
||||
Signal received at sb_2__6_ at 88
|
||||
Signal received at cbx_2__6_ at 32
|
||||
Signal received at sb_1__6_ at 88
|
||||
Signal received at cbx_1__6_ at 32
|
||||
Signal received at sb_0__6_ at 82
|
||||
Signal received at cby_0__6_ at 3
|
||||
Signal received at grid_clb_1__6_ at 116
|
||||
Signal received at cby_1__6_ at 32
|
||||
Signal received at grid_clb_2__6_ at 116
|
||||
Signal received at cby_2__6_ at 32
|
||||
Signal received at grid_clb_3__6_ at 116
|
||||
Signal received at cby_3__6_ at 32
|
||||
Signal received at grid_clb_4__6_ at 116
|
||||
Signal received at cby_4__6_ at 32
|
||||
Signal received at grid_clb_5__6_ at 116
|
||||
Signal received at cby_5__6_ at 32
|
||||
Signal received at grid_clb_6__6_ at 116
|
||||
Signal received at cby_6__6_ at 32
|
||||
Signal received at grid_clb_7__6_ at 116
|
||||
Signal received at cby_7__6_ at 32
|
||||
Signal received at grid_clb_8__6_ at 116
|
||||
Signal received at cby_8__6_ at 32
|
||||
Signal received at grid_clb_9__6_ at 116
|
||||
Signal received at cby_9__6_ at 32
|
||||
Signal received at grid_clb_10__6_ at 116
|
||||
Signal received at cby_10__6_ at 32
|
||||
Signal received at grid_clb_11__6_ at 116
|
||||
Signal received at cby_11__6_ at 32
|
||||
Signal received at grid_clb_12__6_ at 116
|
||||
Signal received at cby_12__6_ at 35
|
||||
Signal received at sb_12__5_ at 83
|
||||
Signal received at cbx_12__5_ at 32
|
||||
Signal received at sb_11__5_ at 88
|
||||
Signal received at cbx_11__5_ at 32
|
||||
Signal received at sb_10__5_ at 88
|
||||
Signal received at cbx_10__5_ at 32
|
||||
Signal received at sb_9__5_ at 88
|
||||
Signal received at cbx_9__5_ at 32
|
||||
Signal received at sb_8__5_ at 88
|
||||
Signal received at cbx_8__5_ at 32
|
||||
Signal received at sb_7__5_ at 88
|
||||
Signal received at cbx_7__5_ at 32
|
||||
Signal received at sb_6__5_ at 88
|
||||
Signal received at cbx_6__5_ at 32
|
||||
Signal received at sb_5__5_ at 88
|
||||
Signal received at cbx_5__5_ at 32
|
||||
Signal received at sb_4__5_ at 88
|
||||
Signal received at cbx_4__5_ at 32
|
||||
Signal received at sb_3__5_ at 88
|
||||
Signal received at cbx_3__5_ at 32
|
||||
Signal received at sb_2__5_ at 88
|
||||
Signal received at cbx_2__5_ at 32
|
||||
Signal received at sb_1__5_ at 88
|
||||
Signal received at cbx_1__5_ at 32
|
||||
Signal received at sb_0__5_ at 82
|
||||
Signal received at cby_0__5_ at 3
|
||||
Signal received at grid_clb_1__5_ at 116
|
||||
Signal received at cby_1__5_ at 32
|
||||
Signal received at grid_clb_2__5_ at 116
|
||||
Signal received at cby_2__5_ at 32
|
||||
Signal received at grid_clb_3__5_ at 116
|
||||
Signal received at cby_3__5_ at 32
|
||||
Signal received at grid_clb_4__5_ at 116
|
||||
Signal received at cby_4__5_ at 32
|
||||
Signal received at grid_clb_5__5_ at 116
|
||||
Signal received at cby_5__5_ at 32
|
||||
Signal received at grid_clb_6__5_ at 116
|
||||
Signal received at cby_6__5_ at 32
|
||||
Signal received at grid_clb_7__5_ at 116
|
||||
Signal received at cby_7__5_ at 32
|
||||
Signal received at grid_clb_8__5_ at 116
|
||||
Signal received at cby_8__5_ at 32
|
||||
Signal received at grid_clb_9__5_ at 116
|
||||
Signal received at cby_9__5_ at 32
|
||||
Signal received at grid_clb_10__5_ at 116
|
||||
Signal received at cby_10__5_ at 32
|
||||
Signal received at grid_clb_11__5_ at 116
|
||||
Signal received at cby_11__5_ at 32
|
||||
Signal received at grid_clb_12__5_ at 116
|
||||
Signal received at cby_12__5_ at 35
|
||||
Signal received at sb_12__4_ at 83
|
||||
Signal received at cbx_12__4_ at 32
|
||||
Signal received at sb_11__4_ at 88
|
||||
Signal received at cbx_11__4_ at 32
|
||||
Signal received at sb_10__4_ at 88
|
||||
Signal received at cbx_10__4_ at 32
|
||||
Signal received at sb_9__4_ at 88
|
||||
Signal received at cbx_9__4_ at 32
|
||||
Signal received at sb_8__4_ at 88
|
||||
Signal received at cbx_8__4_ at 32
|
||||
Signal received at sb_7__4_ at 88
|
||||
Signal received at cbx_7__4_ at 32
|
||||
Signal received at sb_6__4_ at 88
|
||||
Signal received at cbx_6__4_ at 32
|
||||
Signal received at sb_5__4_ at 88
|
||||
Signal received at cbx_5__4_ at 32
|
||||
Signal received at sb_4__4_ at 88
|
||||
Signal received at cbx_4__4_ at 32
|
||||
Signal received at sb_3__4_ at 88
|
||||
Signal received at cbx_3__4_ at 32
|
||||
Signal received at sb_2__4_ at 88
|
||||
Signal received at cbx_2__4_ at 32
|
||||
Signal received at sb_1__4_ at 88
|
||||
Signal received at cbx_1__4_ at 32
|
||||
Signal received at sb_0__4_ at 82
|
||||
Signal received at cby_0__4_ at 3
|
||||
Signal received at grid_clb_1__4_ at 116
|
||||
Signal received at cby_1__4_ at 32
|
||||
Signal received at grid_clb_2__4_ at 116
|
||||
Signal received at cby_2__4_ at 32
|
||||
Signal received at grid_clb_3__4_ at 116
|
||||
Signal received at cby_3__4_ at 32
|
||||
Signal received at grid_clb_4__4_ at 116
|
||||
Signal received at cby_4__4_ at 32
|
||||
Signal received at grid_clb_5__4_ at 116
|
||||
Signal received at cby_5__4_ at 32
|
||||
Signal received at grid_clb_6__4_ at 116
|
||||
Signal received at cby_6__4_ at 32
|
||||
Signal received at grid_clb_7__4_ at 116
|
||||
Signal received at cby_7__4_ at 32
|
||||
Signal received at grid_clb_8__4_ at 116
|
||||
Signal received at cby_8__4_ at 32
|
||||
Signal received at grid_clb_9__4_ at 116
|
||||
Signal received at cby_9__4_ at 32
|
||||
Signal received at grid_clb_10__4_ at 116
|
||||
Signal received at cby_10__4_ at 32
|
||||
Signal received at grid_clb_11__4_ at 116
|
||||
Signal received at cby_11__4_ at 32
|
||||
Signal received at grid_clb_12__4_ at 116
|
||||
Signal received at cby_12__4_ at 35
|
||||
Signal received at sb_12__3_ at 83
|
||||
Signal received at cbx_12__3_ at 32
|
||||
Signal received at sb_11__3_ at 88
|
||||
Signal received at cbx_11__3_ at 32
|
||||
Signal received at sb_10__3_ at 88
|
||||
Signal received at cbx_10__3_ at 32
|
||||
Signal received at sb_9__3_ at 88
|
||||
Signal received at cbx_9__3_ at 32
|
||||
Signal received at sb_8__3_ at 88
|
||||
Signal received at cbx_8__3_ at 32
|
||||
Signal received at sb_7__3_ at 88
|
||||
Signal received at cbx_7__3_ at 32
|
||||
Signal received at sb_6__3_ at 88
|
||||
Signal received at cbx_6__3_ at 32
|
||||
Signal received at sb_5__3_ at 88
|
||||
Signal received at cbx_5__3_ at 32
|
||||
Signal received at sb_4__3_ at 88
|
||||
Signal received at cbx_4__3_ at 32
|
||||
Signal received at sb_3__3_ at 88
|
||||
Signal received at cbx_3__3_ at 32
|
||||
Signal received at sb_2__3_ at 88
|
||||
Signal received at cbx_2__3_ at 32
|
||||
Signal received at sb_1__3_ at 88
|
||||
Signal received at cbx_1__3_ at 32
|
||||
Signal received at sb_0__3_ at 82
|
||||
Signal received at cby_0__3_ at 3
|
||||
Signal received at grid_clb_1__3_ at 116
|
||||
Signal received at cby_1__3_ at 32
|
||||
Signal received at grid_clb_2__3_ at 116
|
||||
Signal received at cby_2__3_ at 32
|
||||
Signal received at grid_clb_3__3_ at 116
|
||||
Signal received at cby_3__3_ at 32
|
||||
Signal received at grid_clb_4__3_ at 116
|
||||
Signal received at cby_4__3_ at 32
|
||||
Signal received at grid_clb_5__3_ at 116
|
||||
Signal received at cby_5__3_ at 32
|
||||
Signal received at grid_clb_6__3_ at 116
|
||||
Signal received at cby_6__3_ at 32
|
||||
Signal received at grid_clb_7__3_ at 116
|
||||
Signal received at cby_7__3_ at 32
|
||||
Signal received at grid_clb_8__3_ at 116
|
||||
Signal received at cby_8__3_ at 32
|
||||
Signal received at grid_clb_9__3_ at 116
|
||||
Signal received at cby_9__3_ at 32
|
||||
Signal received at grid_clb_10__3_ at 116
|
||||
Signal received at cby_10__3_ at 32
|
||||
Signal received at grid_clb_11__3_ at 116
|
||||
Signal received at cby_11__3_ at 32
|
||||
Signal received at grid_clb_12__3_ at 116
|
||||
Signal received at cby_12__3_ at 35
|
||||
Signal received at sb_12__2_ at 83
|
||||
Signal received at cbx_12__2_ at 32
|
||||
Signal received at sb_11__2_ at 88
|
||||
Signal received at cbx_11__2_ at 32
|
||||
Signal received at sb_10__2_ at 88
|
||||
Signal received at cbx_10__2_ at 32
|
||||
Signal received at sb_9__2_ at 88
|
||||
Signal received at cbx_9__2_ at 32
|
||||
Signal received at sb_8__2_ at 88
|
||||
Signal received at cbx_8__2_ at 32
|
||||
Signal received at sb_7__2_ at 88
|
||||
Signal received at cbx_7__2_ at 32
|
||||
Signal received at sb_6__2_ at 88
|
||||
Signal received at cbx_6__2_ at 32
|
||||
Signal received at sb_5__2_ at 88
|
||||
Signal received at cbx_5__2_ at 32
|
||||
Signal received at sb_4__2_ at 88
|
||||
Signal received at cbx_4__2_ at 32
|
||||
Signal received at sb_3__2_ at 88
|
||||
Signal received at cbx_3__2_ at 32
|
||||
Signal received at sb_2__2_ at 88
|
||||
Signal received at cbx_2__2_ at 32
|
||||
Signal received at sb_1__2_ at 88
|
||||
Signal received at cbx_1__2_ at 32
|
||||
Signal received at sb_0__2_ at 82
|
||||
Signal received at cby_0__2_ at 3
|
||||
Signal received at grid_clb_1__2_ at 116
|
||||
Signal received at cby_1__2_ at 32
|
||||
Signal received at grid_clb_2__2_ at 116
|
||||
Signal received at cby_2__2_ at 32
|
||||
Signal received at grid_clb_3__2_ at 116
|
||||
Signal received at cby_3__2_ at 32
|
||||
Signal received at grid_clb_4__2_ at 116
|
||||
Signal received at cby_4__2_ at 32
|
||||
Signal received at grid_clb_5__2_ at 116
|
||||
Signal received at cby_5__2_ at 32
|
||||
Signal received at grid_clb_6__2_ at 116
|
||||
Signal received at cby_6__2_ at 32
|
||||
Signal received at grid_clb_7__2_ at 116
|
||||
Signal received at cby_7__2_ at 32
|
||||
Signal received at grid_clb_8__2_ at 116
|
||||
Signal received at cby_8__2_ at 32
|
||||
Signal received at grid_clb_9__2_ at 116
|
||||
Signal received at cby_9__2_ at 32
|
||||
Signal received at grid_clb_10__2_ at 116
|
||||
Signal received at cby_10__2_ at 32
|
||||
Signal received at grid_clb_11__2_ at 116
|
||||
Signal received at cby_11__2_ at 32
|
||||
Signal received at grid_clb_12__2_ at 116
|
||||
Signal received at cby_12__2_ at 35
|
||||
Signal received at sb_12__1_ at 83
|
||||
Signal received at cbx_12__1_ at 32
|
||||
Signal received at sb_11__1_ at 88
|
||||
Signal received at cbx_11__1_ at 32
|
||||
Signal received at sb_10__1_ at 88
|
||||
Signal received at cbx_10__1_ at 32
|
||||
Signal received at sb_9__1_ at 88
|
||||
Signal received at cbx_9__1_ at 32
|
||||
Signal received at sb_8__1_ at 88
|
||||
Signal received at cbx_8__1_ at 32
|
||||
Signal received at sb_7__1_ at 88
|
||||
Signal received at cbx_7__1_ at 32
|
||||
Signal received at sb_6__1_ at 88
|
||||
Signal received at cbx_6__1_ at 32
|
||||
Signal received at sb_5__1_ at 88
|
||||
Signal received at cbx_5__1_ at 32
|
||||
Signal received at sb_4__1_ at 88
|
||||
Signal received at cbx_4__1_ at 32
|
||||
Signal received at sb_3__1_ at 88
|
||||
Signal received at cbx_3__1_ at 32
|
||||
Signal received at sb_2__1_ at 88
|
||||
Signal received at cbx_2__1_ at 32
|
||||
Signal received at sb_1__1_ at 88
|
||||
Signal received at cbx_1__1_ at 32
|
||||
Signal received at sb_0__1_ at 82
|
||||
Signal received at cby_0__1_ at 3
|
||||
Signal received at grid_clb_1__1_ at 116
|
||||
Signal received at cby_1__1_ at 32
|
||||
Signal received at grid_clb_2__1_ at 116
|
||||
Signal received at cby_2__1_ at 32
|
||||
Signal received at grid_clb_3__1_ at 116
|
||||
Signal received at cby_3__1_ at 32
|
||||
Signal received at grid_clb_4__1_ at 116
|
||||
Signal received at cby_4__1_ at 32
|
||||
Signal received at grid_clb_5__1_ at 116
|
||||
Signal received at cby_5__1_ at 32
|
||||
Signal received at grid_clb_6__1_ at 116
|
||||
Signal received at cby_6__1_ at 32
|
||||
Signal received at grid_clb_7__1_ at 116
|
||||
Signal received at cby_7__1_ at 32
|
||||
Signal received at grid_clb_8__1_ at 116
|
||||
Signal received at cby_8__1_ at 32
|
||||
Signal received at grid_clb_9__1_ at 116
|
||||
Signal received at cby_9__1_ at 32
|
||||
Signal received at grid_clb_10__1_ at 116
|
||||
Signal received at cby_10__1_ at 32
|
||||
Signal received at grid_clb_11__1_ at 116
|
||||
Signal received at cby_11__1_ at 32
|
||||
Signal received at grid_clb_12__1_ at 116
|
||||
Signal received at cby_12__1_ at 35
|
||||
Signal received at sb_12__0_ at 65
|
||||
Signal received at cbx_12__0_ at 23
|
||||
Signal received at sb_11__0_ at 80
|
||||
Signal received at cbx_11__0_ at 23
|
||||
Signal received at sb_10__0_ at 80
|
||||
Signal received at cbx_10__0_ at 23
|
||||
Signal received at sb_9__0_ at 80
|
||||
Signal received at cbx_9__0_ at 23
|
||||
Signal received at sb_8__0_ at 80
|
||||
Signal received at cbx_8__0_ at 23
|
||||
Signal received at sb_7__0_ at 80
|
||||
Signal received at cbx_7__0_ at 23
|
||||
Signal received at sb_6__0_ at 80
|
||||
Signal received at cbx_6__0_ at 23
|
||||
Signal received at sb_5__0_ at 80
|
||||
Signal received at cbx_5__0_ at 23
|
||||
Signal received at sb_4__0_ at 80
|
||||
Signal received at cbx_4__0_ at 23
|
||||
Signal received at sb_3__0_ at 80
|
||||
Signal received at cbx_3__0_ at 23
|
||||
Signal received at sb_2__0_ at 80
|
||||
Signal received at cbx_2__0_ at 23
|
||||
Signal received at sb_1__0_ at 80
|
||||
Signal received at cbx_1__0_ at 23
|
||||
Signal received at sb_0__0_ at 41
|
||||
Simulation Finished in clocks 40726
|
||||
Test Passed: ConfigChainTestFull
|
||||
Passed 1 tests (0 skipped)
|
||||
***************************************************************************************************
|
||||
** TEST PASS/FAIL SIM TIME(NS) REAL TIME(S) RATIO(NS/S) **
|
||||
***************************************************************************************************
|
||||
** fpga_reset_hd_sky_pnr.ConfigChainTestFull PASS 407320.00 96.06 4240.25 **
|
||||
***************************************************************************************************
|
||||
|
||||
*************************************************************************************
|
||||
** ERRORS : 0 **
|
||||
*************************************************************************************
|
||||
** SIM TIME : 407320.00 NS **
|
||||
** REAL TIME : 96.11 S **
|
||||
** SIM / REAL TIME : 4237.94 NS/S **
|
||||
*************************************************************************************
|
||||
|
||||
Shutting down...
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
|
||||
initial begin
|
||||
$dumpfile ("ccff_test.vcd");
|
||||
$dumpvars (1,
|
||||
io_in[37],
|
||||
io_in[36],
|
||||
fpga_core_uut.prog_clk,
|
||||
fpga_core_uut.Reset,
|
||||
fpga_core_uut.pReset,
|
||||
fpga_core_uut.sb_12__12_.ccff_head,
|
||||
fpga_core_uut.sb_12__12_.ccff_tail,
|
||||
fpga_core_uut.ccff_head,
|
||||
fpga_core_uut.ccff_tail
|
||||
);
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpvars (0,
|
||||
fpga_core_uut.sb_12__12_,
|
||||
fpga_core_uut.sb_6__0_
|
||||
);
|
||||
end
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
|
||||
initial begin
|
||||
$dumpfile ("scff_test.vcd");
|
||||
$dumpvars (1,
|
||||
io_in[37],
|
||||
io_in[36],
|
||||
io_in[0],
|
||||
fpga_core_uut.scff_Wires,
|
||||
fpga_core_uut.Test_en,
|
||||
|
||||
fpga_core_uut.sb_0__12_.SC_IN_TOP,
|
||||
fpga_core_uut.sb_0__12_.SC_OUT_BOT,
|
||||
fpga_core_uut.grid_clb_1__12_.SC_IN_TOP,
|
||||
fpga_core_uut.grid_clb_1__12_.SC_OUT_BOT,
|
||||
sc_head,
|
||||
sc_tail
|
||||
);
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpvars (0,
|
||||
fpga_core_uut.sb_12__12_);
|
||||
end
|
||||
|
|
@ -0,0 +1,617 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
`define FUNCTIONAL 1
|
||||
`define UNIT_DELAY #0.01
|
||||
|
||||
`include "./TaskConfigCopy/FPGA1212_SOFA_CHD_task/sc_verilog/fd_hd_mux_custom_cells_tt.v"
|
||||
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_12.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_6.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/diode/sky130_fd_sc_hd__diode_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/diode/sky130_fd_sc_hd__diode.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbp/sky130_fd_sc_hd__dlxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbp/sky130_fd_sc_hd__dlxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtp/sky130_fd_sc_hd__dlxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtp/sky130_fd_sc_hd__dlxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxbp/sky130_fd_sc_hd__edfxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxbp/sky130_fd_sc_hd__edfxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxtp/sky130_fd_sc_hd__edfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxtp/sky130_fd_sc_hd__edfxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_0.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcin/sky130_fd_sc_hd__fahcin_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcin/sky130_fd_sc_hd__fahcin.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcon/sky130_fd_sc_hd__fahcon_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcon/sky130_fd_sc_hd__fahcon.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fah/sky130_fd_sc_hd__fah_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fah/sky130_fd_sc_hd__fah.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv.v"
|
||||
//
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_8.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd/sky130_fd_sc_hd__tapvgnd_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
|
||||
|
||||
//
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b.v"
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_1.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_2.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_4.v"
|
||||
`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4.v"
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
|
||||
initial begin
|
||||
$dumpfile ("ccff_test.vcd");
|
||||
$dumpvars (1, prog_clk_pad,
|
||||
prog_clk,
|
||||
ccff_head_pad,
|
||||
ccff_head,
|
||||
fpga_core_uut.sb_2__2_.ccff_tail,
|
||||
fpga_core_uut.cbx_2__2_.ccff_tail,
|
||||
fpga_core_uut.grid_io_top_2__3_.ccff_tail,
|
||||
fpga_core_uut.sb_1__2_.ccff_tail,
|
||||
fpga_core_uut.cbx_1__2_.ccff_tail,
|
||||
fpga_core_uut.grid_io_top_1__3_.ccff_tail,
|
||||
fpga_core_uut.sb_0__2_.ccff_tail,
|
||||
fpga_core_uut.cby_0__2_.ccff_tail,
|
||||
fpga_core_uut.grid_io_left_0__2_.ccff_tail,
|
||||
fpga_core_uut.grid_clb_1__2_.ccff_tail,
|
||||
fpga_core_uut.cby_1__2_.ccff_tail,
|
||||
fpga_core_uut.grid_clb_2__2_.ccff_tail,
|
||||
fpga_core_uut.cby_2__2_.ccff_tail,
|
||||
fpga_core_uut.grid_io_right_3__2_.ccff_tail,
|
||||
fpga_core_uut.sb_2__1_.ccff_tail,
|
||||
fpga_core_uut.cbx_2__1_.ccff_tail,
|
||||
fpga_core_uut.sb_1__1_.ccff_tail,
|
||||
fpga_core_uut.cbx_1__1_.ccff_tail,
|
||||
fpga_core_uut.sb_0__1_.ccff_tail,
|
||||
fpga_core_uut.cby_0__1_.ccff_tail,
|
||||
fpga_core_uut.grid_io_left_0__1_.ccff_tail,
|
||||
fpga_core_uut.grid_clb_1__1_.ccff_tail,
|
||||
fpga_core_uut.cby_1__1_.ccff_tail,
|
||||
fpga_core_uut.grid_clb_2__1_.ccff_tail,
|
||||
fpga_core_uut.cby_2__1_.ccff_tail,
|
||||
fpga_core_uut.grid_io_right_3__1_.ccff_tail,
|
||||
fpga_core_uut.sb_2__0_.ccff_tail,
|
||||
fpga_core_uut.cbx_2__0_.ccff_tail,
|
||||
fpga_core_uut.grid_io_bottom_2__0_.ccff_tail,
|
||||
fpga_core_uut.sb_1__0_.ccff_tail,
|
||||
fpga_core_uut.cbx_1__0_.ccff_tail,
|
||||
fpga_core_uut.grid_io_bottom_1__0_.ccff_tail,
|
||||
fpga_core_uut.sb_0__0_.ccff_tail,
|
||||
ccff_tail_pad,
|
||||
ccff_tail);
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
|
||||
## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
## Verification makefile for FPGA1212_RESET_HD_SKY_PNR (Caravel-QLSOFA-HD)
|
||||
## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
SHELL=bash
|
||||
PYTHON_EXEC=python3.8
|
||||
RERUN = 0
|
||||
TB = top
|
||||
OPTIONS =
|
||||
SIM = modelsim
|
||||
TEST_FILE = fpga_reset_hd_sky_pnr
|
||||
|
||||
.SILENT:
|
||||
.ONESHELL:
|
||||
|
||||
## Copy all the POSTPnR files from realease directory
|
||||
UpdatePostPnRNetlist:
|
||||
source ../config.sh
|
||||
DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
|
||||
echo "Collecting files $${DESIGN_NAME}"
|
||||
cp ../pnr/$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || \
|
||||
cp ../$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || :
|
||||
|
||||
|
||||
## Create symbolic links and run test
|
||||
RunPostPnRTest:
|
||||
source ../config.sh
|
||||
INCLUDE_POSTPNR=$${INCLUDE_POSTPNR:-include_postpnr}
|
||||
DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
|
||||
VerificationFile=$${TEST_FILE:-${TEST_FILE}}
|
||||
# = = = = = = = = = = = = = = Log Information = = = = = = = = = = = =
|
||||
echo "DESIGN_NAME = $${DESIGN_NAME}"
|
||||
echo "VerificationFile = $${DESIGN_NAME}"
|
||||
echo "INCLUDE_FILE = $${INCLUDE_POSTPNR}"
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
echo $${VerificationFile}
|
||||
if [ ! -f "./$${VerificationFile}.py" ]; then
|
||||
echo "Test file not found $${VerificationFile}.py"
|
||||
fi
|
||||
echo "Using test file $${VerificationFile}.py"
|
||||
Tests=`grep -A 1 "^@cocotb.test" ./$${VerificationFile}.py | grep "def" | sed "s/.*def \(.*\)(.*/\1/g"`
|
||||
select RUN_TB in $${Tests}
|
||||
do
|
||||
echo "Running $${RUN_TB} Test"
|
||||
if [[ -d "$${RUN_TB}_run" ]] && [[ -z "$${RERUN}" ]]; then
|
||||
echo "Skipping copying source, which will skip the compilations";
|
||||
cp *_tests.py ./$${RUN_TB}_run;
|
||||
cd $${RUN_TB}_run; break;
|
||||
fi
|
||||
|
||||
# = = = = = = = = = = = Prepare Netlist = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = Copy python test = = = = = = = = = = = = =
|
||||
mkdir -p "$${RUN_TB}_run"
|
||||
cp $${VerificationFile}.py ./$${RUN_TB}_run
|
||||
cp $${DESIGN_NAME}_icv_in_design.pt.v ./$${RUN_TB}_run/$${DESIGN_NAME}_cocosim.v
|
||||
|
||||
TaskDir=`readlink -f ../*_Verilog/TaskConfigCopy`
|
||||
TaskDir2=`readlink -f ../*_task`
|
||||
if [ -d "$$TaskDir" ]; then
|
||||
rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run
|
||||
elif [ -d "$$TaskDir2" ]; then
|
||||
TaskDir=`readlink -f ../*_task`
|
||||
rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run/TaskConfigCopy
|
||||
else
|
||||
echo "Task configuration directory not found"
|
||||
fi
|
||||
# = = = = = = = = = = = Enter Run Directory = = = = = = = = = = = = =
|
||||
cd $${RUN_TB}_run
|
||||
cp ../INIT/$${INCLUDE_POSTPNR}.v ./fabric_netlists_cocosim.v
|
||||
echo "\`include \"$$(readlink -f $${DESIGN_NAME}_cocosim.v)\"" >> ./fabric_netlists_cocosim.v
|
||||
|
||||
# = = = = = = = = = = = Insert Init Signals = = = = = = = = = = = =
|
||||
if test -f "../INIT/$${RUN_TB}_init.v"; then
|
||||
echo "Found Initialization file [../INIT/$${RUN_TB}_init.v]"
|
||||
modLineNo=$$(grep -n "module fpga_top" $${DESIGN_NAME}_cocosim.v | cut -f1 -d:)
|
||||
echo $${modLineNo}
|
||||
sed -i "$${modLineNo},\$${/endmodule/d}" $${DESIGN_NAME}_cocosim.v
|
||||
cat ../INIT/$${RUN_TB}_init.v >> $${DESIGN_NAME}_cocosim.v
|
||||
printf "\nendmodule" >> $${DESIGN_NAME}_cocosim.v
|
||||
else
|
||||
echo "No Initialization file found [../INIT/$${RUN_TB}_init.v]"
|
||||
fi
|
||||
|
||||
# = = = = = = = = Create Makefile to run = = = = = = = = = = = = = =
|
||||
echo "TOPLEVEL_LANG = verilog" > Makefile
|
||||
echo "VERILOG_SOURCES = fabric_netlists_cocosim.v" >> Makefile
|
||||
echo "TOPLEVEL = $${DESIGN_NAME}" >> Makefile
|
||||
echo "MODULE = $${VerificationFile}" >> Makefile
|
||||
echo "TESTCASE = $${RUN_TB}" >> Makefile
|
||||
echo "" >> Makefile
|
||||
echo "include $(shell cocotb-config --makefiles)/Makefile.sim" >> Makefile
|
||||
break
|
||||
done
|
||||
if [ -z "$$DRY_RUN" ]; then make SIM=$${SIM:-${SIM}}; fi
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
Found test fpga_reset_hd_sky_pnr.ScanChainTestFull
|
||||
Running test 1/1: ScanChainTestFull
|
||||
Starting test: "ScanChainTestFull"
|
||||
Description: None
|
||||
Signal received at grid_clb_1__12_ at 8
|
||||
Signal received at grid_clb_1__11_ at 8
|
||||
Signal received at grid_clb_1__10_ at 8
|
||||
Signal received at grid_clb_1__9_ at 8
|
||||
Signal received at grid_clb_1__8_ at 8
|
||||
Signal received at grid_clb_1__7_ at 8
|
||||
Signal received at grid_clb_1__6_ at 8
|
||||
Signal received at grid_clb_1__5_ at 8
|
||||
Signal received at grid_clb_1__4_ at 8
|
||||
Signal received at grid_clb_1__3_ at 8
|
||||
Signal received at grid_clb_1__2_ at 8
|
||||
Signal received at grid_clb_1__1_ at 8
|
||||
Signal received at grid_clb_2__1_ at 8
|
||||
Signal received at grid_clb_2__2_ at 8
|
||||
Signal received at grid_clb_2__3_ at 8
|
||||
Signal received at grid_clb_2__4_ at 8
|
||||
Signal received at grid_clb_2__5_ at 8
|
||||
Signal received at grid_clb_2__6_ at 8
|
||||
Signal received at grid_clb_2__7_ at 8
|
||||
Signal received at grid_clb_2__8_ at 8
|
||||
Signal received at grid_clb_2__9_ at 8
|
||||
Signal received at grid_clb_2__10_ at 8
|
||||
Signal received at grid_clb_2__11_ at 8
|
||||
Signal received at grid_clb_2__12_ at 8
|
||||
Signal received at grid_clb_3__12_ at 8
|
||||
Signal received at grid_clb_3__11_ at 9
|
||||
Signal received at grid_clb_3__10_ at 8
|
||||
Signal received at grid_clb_3__9_ at 8
|
||||
Signal received at grid_clb_3__8_ at 8
|
||||
Signal received at grid_clb_3__7_ at 8
|
||||
Signal received at grid_clb_3__6_ at 8
|
||||
Signal received at grid_clb_3__5_ at 8
|
||||
Signal received at grid_clb_3__4_ at 8
|
||||
Signal received at grid_clb_3__3_ at 8
|
||||
Signal received at grid_clb_3__2_ at 8
|
||||
Signal received at grid_clb_3__1_ at 8
|
||||
Signal received at grid_clb_4__1_ at 8
|
||||
Signal received at grid_clb_4__2_ at 8
|
||||
Signal received at grid_clb_4__3_ at 8
|
||||
Signal received at grid_clb_4__4_ at 8
|
||||
Signal received at grid_clb_4__5_ at 8
|
||||
Signal received at grid_clb_4__6_ at 8
|
||||
Signal received at grid_clb_4__7_ at 8
|
||||
Signal received at grid_clb_4__8_ at 8
|
||||
Signal received at grid_clb_4__9_ at 8
|
||||
Signal received at grid_clb_4__10_ at 8
|
||||
Signal received at grid_clb_4__11_ at 8
|
||||
Signal received at grid_clb_4__12_ at 8
|
||||
Signal received at grid_clb_5__12_ at 8
|
||||
Signal received at grid_clb_5__11_ at 8
|
||||
Signal received at grid_clb_5__10_ at 8
|
||||
Signal received at grid_clb_5__9_ at 8
|
||||
Signal received at grid_clb_5__8_ at 8
|
||||
Signal received at grid_clb_5__7_ at 8
|
||||
Signal received at grid_clb_5__6_ at 8
|
||||
Signal received at grid_clb_5__5_ at 8
|
||||
Signal received at grid_clb_5__4_ at 8
|
||||
Signal received at grid_clb_5__3_ at 8
|
||||
Signal received at grid_clb_5__2_ at 8
|
||||
Signal received at grid_clb_5__1_ at 8
|
||||
Signal received at grid_clb_6__1_ at 8
|
||||
Signal received at grid_clb_6__2_ at 8
|
||||
Signal received at grid_clb_6__3_ at 8
|
||||
Signal received at grid_clb_6__4_ at 8
|
||||
Signal received at grid_clb_6__5_ at 8
|
||||
Signal received at grid_clb_6__6_ at 8
|
||||
Signal received at grid_clb_6__7_ at 8
|
||||
Signal received at grid_clb_6__8_ at 8
|
||||
Signal received at grid_clb_6__9_ at 8
|
||||
Signal received at grid_clb_6__10_ at 8
|
||||
Signal received at grid_clb_6__11_ at 8
|
||||
Signal received at grid_clb_6__12_ at 8
|
||||
Signal received at grid_clb_7__12_ at 8
|
||||
Signal received at grid_clb_7__11_ at 8
|
||||
Signal received at grid_clb_7__10_ at 8
|
||||
Signal received at grid_clb_7__9_ at 8
|
||||
Signal received at grid_clb_7__8_ at 8
|
||||
Signal received at grid_clb_7__7_ at 8
|
||||
Signal received at grid_clb_7__6_ at 8
|
||||
Signal received at grid_clb_7__5_ at 8
|
||||
Signal received at grid_clb_7__4_ at 8
|
||||
Signal received at grid_clb_7__3_ at 8
|
||||
Signal received at grid_clb_7__2_ at 8
|
||||
Signal received at grid_clb_7__1_ at 8
|
||||
Signal received at grid_clb_8__1_ at 8
|
||||
Signal received at grid_clb_8__2_ at 8
|
||||
Signal received at grid_clb_8__3_ at 8
|
||||
Signal received at grid_clb_8__4_ at 8
|
||||
Signal received at grid_clb_8__5_ at 8
|
||||
Signal received at grid_clb_8__6_ at 8
|
||||
Signal received at grid_clb_8__7_ at 8
|
||||
Signal received at grid_clb_8__8_ at 8
|
||||
Signal received at grid_clb_8__9_ at 8
|
||||
Signal received at grid_clb_8__10_ at 8
|
||||
Signal received at grid_clb_8__11_ at 8
|
||||
Signal received at grid_clb_8__12_ at 8
|
||||
Signal received at grid_clb_9__12_ at 8
|
||||
Signal received at grid_clb_9__11_ at 8
|
||||
Signal received at grid_clb_9__10_ at 8
|
||||
Signal received at grid_clb_9__9_ at 8
|
||||
Signal received at grid_clb_9__8_ at 8
|
||||
Signal received at grid_clb_9__7_ at 8
|
||||
Signal received at grid_clb_9__6_ at 8
|
||||
Signal received at grid_clb_9__5_ at 8
|
||||
Signal received at grid_clb_9__4_ at 8
|
||||
Signal received at grid_clb_9__3_ at 8
|
||||
Signal received at grid_clb_9__2_ at 8
|
||||
Signal received at grid_clb_9__1_ at 8
|
||||
Signal received at grid_clb_10__1_ at 8
|
||||
Signal received at grid_clb_10__2_ at 8
|
||||
Signal received at grid_clb_10__3_ at 8
|
||||
Signal received at grid_clb_10__4_ at 8
|
||||
Signal received at grid_clb_10__5_ at 8
|
||||
Signal received at grid_clb_10__6_ at 8
|
||||
Signal received at grid_clb_10__7_ at 8
|
||||
Signal received at grid_clb_10__8_ at 8
|
||||
Signal received at grid_clb_10__9_ at 8
|
||||
Signal received at grid_clb_10__10_ at 8
|
||||
Signal received at grid_clb_10__11_ at 8
|
||||
Signal received at grid_clb_10__12_ at 8
|
||||
Signal received at grid_clb_11__12_ at 8
|
||||
Signal received at grid_clb_11__11_ at 8
|
||||
Signal received at grid_clb_11__10_ at 8
|
||||
Signal received at grid_clb_11__9_ at 8
|
||||
Signal received at grid_clb_11__8_ at 8
|
||||
Signal received at grid_clb_11__7_ at 8
|
||||
Signal received at grid_clb_11__6_ at 8
|
||||
Signal received at grid_clb_11__5_ at 8
|
||||
Signal received at grid_clb_11__4_ at 8
|
||||
Signal received at grid_clb_11__3_ at 8
|
||||
Signal received at grid_clb_11__2_ at 8
|
||||
Signal received at grid_clb_11__1_ at 8
|
||||
Signal received at grid_clb_12__1_ at 8
|
||||
Signal received at grid_clb_12__2_ at 8
|
||||
Signal received at grid_clb_12__3_ at 8
|
||||
Signal received at grid_clb_12__4_ at 8
|
||||
Signal received at grid_clb_12__5_ at 8
|
||||
Signal received at grid_clb_12__6_ at 8
|
||||
Signal received at grid_clb_12__7_ at 8
|
||||
Signal received at grid_clb_12__8_ at 8
|
||||
Signal received at grid_clb_12__9_ at 8
|
||||
Signal received at grid_clb_12__10_ at 8
|
||||
Signal received at grid_clb_12__11_ at 8
|
||||
Signal received at grid_clb_12__12_ at 8
|
||||
Simulation Finished in clocks 1152
|
||||
Per Grid 8.0
|
||||
Test Passed: ScanChainTestFull
|
||||
Passed 1 tests (0 skipped)
|
||||
*************************************************************************************************
|
||||
** TEST PASS/FAIL SIM TIME(NS) REAL TIME(S) RATIO(NS/S) **
|
||||
*************************************************************************************************
|
||||
** fpga_reset_hd_sky_pnr.ScanChainTestFull PASS 11580.00 2.35 4936.74 **
|
||||
*************************************************************************************************
|
||||
|
||||
*************************************************************************************
|
||||
** ERRORS : 0 **
|
||||
*************************************************************************************
|
||||
** SIM TIME : 11580.00 NS **
|
||||
** REAL TIME : 2.39 S **
|
||||
** SIM / REAL TIME : 4848.92 NS/S **
|
||||
*************************************************************************************
|
||||
|
||||
Shutting down...
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,349 @@
|
|||
import random
|
||||
import os
|
||||
import sys
|
||||
import glob
|
||||
import math
|
||||
import cocotb
|
||||
import logging
|
||||
import filecmp
|
||||
from logging.handlers import RotatingFileHandler
|
||||
from collections import OrderedDict
|
||||
from pprint import pprint
|
||||
from xml.dom import minidom
|
||||
from cocotb.binary import BinaryValue
|
||||
from cocotb.log import SimLogFormatter
|
||||
from cocotb.clock import Clock
|
||||
from cocotb import wavedrom
|
||||
from cocotb.utils import get_sim_time
|
||||
from cocotb.handle import Force, Release, Deposit
|
||||
from cocotb.monitors import Monitor
|
||||
from cocotb.scoreboard import Scoreboard
|
||||
from cocotb.result import SimTimeoutError, TestFailure, SimTimeoutError, TestSuccess
|
||||
from cocotb.triggers import FallingEdge, RisingEdge, Timer, ClockCycles, with_timeout, First
|
||||
|
||||
root_logger = logging.getLogger()
|
||||
|
||||
|
||||
file_handler = RotatingFileHandler(
|
||||
"run.log", maxBytes=(5 * 1024 * 1024), backupCount=2)
|
||||
root_logger.addHandler(file_handler)
|
||||
|
||||
# Caravel interface pin mapping
|
||||
FromPinAlias = {
|
||||
"prog_clk": "io_in[37]",
|
||||
"clk": "io_in[36]",
|
||||
"pReset": "io_in[3]",
|
||||
"Reset": "io_in[2]",
|
||||
"test_en": "io_in[0]",
|
||||
"sc_head": "io_in[26]",
|
||||
"sc_tail": "io_in[11]",
|
||||
"ccff_head": "io_in[12]",
|
||||
"ccff_tail": "io_in[35]",
|
||||
}
|
||||
|
||||
|
||||
def getFromPinAlias(dut, pinName):
|
||||
''' Get DUT pin from alias '''
|
||||
return eval(f"dut.{FromPinAlias[pinName]}")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def ConfigChainTestFull(dut):
|
||||
# = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = =
|
||||
PConf = getConfig()
|
||||
clk = getFromPinAlias(dut, "clk")
|
||||
prog_clk = getFromPinAlias(dut, "prog_clk")
|
||||
test_en = getFromPinAlias(dut, "test_en")
|
||||
pReset = getFromPinAlias(dut, "pReset")
|
||||
Reset = getFromPinAlias(dut, "Reset")
|
||||
ccff_head = getFromPinAlias(dut, "ccff_head")
|
||||
ccff_tail = getFromPinAlias(dut, "ccff_tail")
|
||||
PCLK_PERIOD = 10 # in nanoseconds
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
clk <= 0 # Disable prog clock
|
||||
Reset <= 0 # Disable reset
|
||||
pReset <= 0 # Reset all configuration FF
|
||||
pclock = Clock(prog_clk, PCLK_PERIOD*0.5, units="ns")
|
||||
cocotb.fork(pclock.start()) # Start the clock
|
||||
|
||||
# Clock Preamble Ticks 2
|
||||
await ClockCycles(prog_clk, 2)
|
||||
await FallingEdge(prog_clk)
|
||||
pReset <= 1
|
||||
|
||||
# Pass 1 bit logic to CCFF chain
|
||||
ccff_head <= 1
|
||||
await FallingEdge(prog_clk)
|
||||
ccff_head <= 0
|
||||
|
||||
# Check CCFF_tail of each module in sequence
|
||||
CCFFChain = filter(lambda x: not "grid_io" in x, CreateCCFFChain())
|
||||
try:
|
||||
start_ccff_time = get_sim_time(units='ns')
|
||||
for ModuleName in CCFFChain:
|
||||
InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.ccff_tail")
|
||||
|
||||
# Wait for tick
|
||||
start_time_ns = get_sim_time(units='ns')
|
||||
await with_timeout(FallingEdge(InstPtr), 200*PCLK_PERIOD, 'ns')
|
||||
edge_time_ns = get_sim_time(units='ns')
|
||||
|
||||
# Verify
|
||||
CLKTick = math.ceil((edge_time_ns-start_time_ns)/PCLK_PERIOD)
|
||||
dut._log.info(
|
||||
f"Signal received at {ModuleName} at {CLKTick}")
|
||||
if (CLKTick != 8):
|
||||
TestFailure(
|
||||
f"Expected 8 ticks on module {ModuleName} received {CLKTick}")
|
||||
end_ccff_time = get_sim_time(units='ns')
|
||||
await ClockCycles(prog_clk, 10)
|
||||
TotalClock = math.ceil((end_ccff_time-start_ccff_time)/PCLK_PERIOD)
|
||||
dut._log.info(f"Simulation Finished in clocks {TotalClock}")
|
||||
except SimTimeoutError:
|
||||
raise TestFailure(f"Failed to receive signal on {ModuleName}")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def ScanChainTestFull(dut):
|
||||
# = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = =
|
||||
PConf = getConfig()
|
||||
clk = getFromPinAlias(dut, "clk")
|
||||
prog_clk = getFromPinAlias(dut, "prog_clk")
|
||||
pReset = getFromPinAlias(dut, "pReset")
|
||||
Reset = getFromPinAlias(dut, "Reset")
|
||||
test_en = getFromPinAlias(dut, "test_en")
|
||||
sc_head = getFromPinAlias(dut, "sc_head")
|
||||
sc_tail = getFromPinAlias(dut, "sc_tail")
|
||||
CLK_PERIOD = 10 # in nanoseconds
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
prog_clk <= 0 # Disable prog clock
|
||||
pReset <= 0 # Disable programming reset
|
||||
Reset <= 0 # Disable reset
|
||||
clock = Clock(clk, CLK_PERIOD*0.5, units="ns")
|
||||
cocotb.fork(clock.start()) # Start the clock
|
||||
|
||||
# Clock Preamble Ticks 2
|
||||
await ClockCycles(clk, 2)
|
||||
|
||||
# Setup control signals
|
||||
await FallingEdge(clk)
|
||||
test_en <= 1
|
||||
Reset <= 1
|
||||
|
||||
# Pass 1 bit logic to SCFF chain
|
||||
sc_head <= 1
|
||||
await FallingEdge(clk)
|
||||
sc_head <= 0
|
||||
|
||||
try:
|
||||
start_scff_time = get_sim_time(units='ns')
|
||||
for X in range(1, 1+PConf["FPGA_SIZE_X"]):
|
||||
Yrange = range(1, 1+PConf["FPGA_SIZE_X"])
|
||||
Yrange = reversed(Yrange) if (X % 2) else Yrange
|
||||
for Y in Yrange:
|
||||
ModuleName = f"grid_clb_{X}__{Y}_"
|
||||
PinName = "SC_OUT_BOT" if (X % 2) else "SC_OUT_TOP"
|
||||
InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.{PinName}")
|
||||
# Wait for tick
|
||||
start_time_ns = get_sim_time(units='ns')
|
||||
await with_timeout(FallingEdge(InstPtr), 50*CLK_PERIOD, 'ns')
|
||||
edge_time_ns = get_sim_time(units='ns')
|
||||
|
||||
# Verify
|
||||
CLKTick = math.ceil((edge_time_ns-start_time_ns)/CLK_PERIOD)
|
||||
dut._log.info(
|
||||
f"Signal received at {ModuleName} at {CLKTick}")
|
||||
if (CLKTick != 8):
|
||||
TestFailure(
|
||||
f"Expected 8 ticks on module {ModuleName} received {CLKTick}")
|
||||
end_scff_time = get_sim_time(units='ns')
|
||||
TotalClock = math.ceil((end_scff_time-start_scff_time)/CLK_PERIOD)
|
||||
await ClockCycles(clk, 10)
|
||||
dut._log.info(f"Simulation Finished in clocks {TotalClock}")
|
||||
dut._log.info(f"Per Grid {TotalClock/(PConf['FPGA_SIZE_X']**2)}")
|
||||
except SimTimeoutError:
|
||||
raise TestFailure(f"Failed to receive signal on {ModuleName}")
|
||||
|
||||
|
||||
# ###================================================================
|
||||
# = = = = = = = = = = Utils Functions = = = = = = = = = = = = = = = =
|
||||
# ###================================================================
|
||||
|
||||
|
||||
def getConfig():
|
||||
"""
|
||||
return config.sh varaibles with default values
|
||||
"""
|
||||
return {
|
||||
"TECHNOLOGY": os.environ.get('TECHNOLOGY', 'skywater'),
|
||||
"PROJ_NAME": os.environ.get('PROJ_NAME', None),
|
||||
"DESIGN_STYLE": os.environ.get('DESIGN_STYLE', "hier"),
|
||||
"FPGA_SIZE_X": int(os.environ.get('FPGA_SIZE_X', 0)),
|
||||
"FPGA_SIZE_Y": int(os.environ.get('FPGA_SIZE_Y', 0)),
|
||||
}
|
||||
|
||||
|
||||
@cocotb.coroutine
|
||||
async def ProgramPhase(dut, BitFile, maxCycles=sys.maxsize):
|
||||
dut.pReset_pad = 0
|
||||
bitCount = 0
|
||||
with open(BitFile, "r") as fp:
|
||||
dut._log.info(f"Bitfile opened : {BitFile}")
|
||||
while bitCount < maxCycles:
|
||||
c = fp.read(1)
|
||||
if not c in ["0", "1"]:
|
||||
dut._log.info(f"Configured device with {bitCount} bits")
|
||||
break
|
||||
bitCount += 1
|
||||
if (bitCount % 50) == 0:
|
||||
dut._log.info(f"Writen {bitCount} bits")
|
||||
dut.ccff_head_pad = int(c)
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
|
||||
|
||||
@cocotb.coroutine
|
||||
async def AutoConfigure(dut, BitFile, ccPaths, BitstreamLen):
|
||||
TotalBitsCount = 0
|
||||
PreviousSync = 0
|
||||
# Locking Signal
|
||||
with open(BitFile, "r") as fp:
|
||||
dut._log.info(f"Bitfile opened {BitFile}")
|
||||
syncPts = math.ceil(BitstreamLen/4800)
|
||||
InitialBits = [int(i) for i in list(fp.read(syncPts+1))]
|
||||
dut._log.info(f"Will make total {syncPts} sync {InitialBits}")
|
||||
for inst, eachModule in ccPaths.items():
|
||||
BitsCount = 0
|
||||
for eachPath in eachModule:
|
||||
size = eachPath["width"]
|
||||
BitsCount += size
|
||||
try:
|
||||
Stream = fp.read(size)
|
||||
bits = int(Stream, 2)
|
||||
except:
|
||||
dut._log.info(f"Padding Zero")
|
||||
bits = 0
|
||||
eachPath["obj"] <= Force(bits)
|
||||
TotalBitsCount += BitsCount
|
||||
dut._log.info(f"Configured {inst} with {BitsCount} bits ")
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
|
||||
# Releasing Signals
|
||||
PreviousSync = 0
|
||||
TotalBitsCount = 0
|
||||
for inst, eachModule in ccPaths.items():
|
||||
for eachPath in eachModule:
|
||||
eachPath["obj"] <= Release()
|
||||
TotalBitsCount += eachPath["width"]
|
||||
if (TotalBitsCount-PreviousSync) > 4800:
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
PreviousSync = TotalBitsCount
|
||||
dut._log.info(f"Releasing config of {inst}")
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
dut._log.info(f"Configured {TotalBitsCount} bits")
|
||||
|
||||
|
||||
def SaveConfiguration(CFFPaths, filename, style="default"):
|
||||
lineW = 0
|
||||
with open(filename, "w") as fp:
|
||||
for _, eachModule in CFFPaths.items():
|
||||
for eachPath in eachModule:
|
||||
val = eachPath["obj"].value.binstr
|
||||
if style == 'default':
|
||||
val = "\n".join(list(val))
|
||||
fp.write(val+"\n")
|
||||
elif style == "bitstream":
|
||||
fp.write(val)
|
||||
elif style == "detailed":
|
||||
fp.write(f"{eachPath['name']} {val}\n")
|
||||
elif style == "adjusted":
|
||||
for eachC in val:
|
||||
fp.write(eachC)
|
||||
lineW += 1
|
||||
if (lineW == 32):
|
||||
fp.write("\n")
|
||||
lineW = 0
|
||||
|
||||
|
||||
def CreateCCFFChain():
|
||||
CCFFChain = []
|
||||
mydoc = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = mydoc.getElementsByTagName('key')
|
||||
for elem in items:
|
||||
CCFFChain.append(elem.attributes['alias'].value)
|
||||
return CCFFChain
|
||||
|
||||
|
||||
def returnPaths(Node, PathList):
|
||||
Nodes = [e for e in Node.childNodes if not isinstance(e, minidom.Text)]
|
||||
# pprint(Nodes)
|
||||
for eachN in Nodes:
|
||||
eachNChild = [
|
||||
e for e in eachN.childNodes if not isinstance(e, minidom.Text)]
|
||||
Bitstream = [e for e in eachNChild if e.tagName == "bitstream"]
|
||||
if Bitstream:
|
||||
Hier = eachN.getElementsByTagName("hierarchy")[0]
|
||||
path = [each.attributes["name"].value
|
||||
for each in Hier.getElementsByTagName("instance")]
|
||||
path = ".".join(path).replace('fpga_top', 'dut.fpga_core_uut')
|
||||
|
||||
bitEles = Bitstream[0].getElementsByTagName("bit")
|
||||
ports = [path + "." + each.attributes["memory_port"].value.split("[")[0]
|
||||
for each in bitEles[:1]]
|
||||
length = len(bitEles)
|
||||
value = "".join([e.attributes["value"].value for e in bitEles])
|
||||
PathList.append({
|
||||
"name": ports[0],
|
||||
"width": length,
|
||||
"value": value
|
||||
})
|
||||
elif eachN.tagName == "bitstream_block":
|
||||
returnPaths(eachN, PathList)
|
||||
|
||||
|
||||
def get_modules():
|
||||
FabricKey = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = FabricKey.getElementsByTagName('key')
|
||||
return [elem.attributes['alias'].value for elem in items]
|
||||
|
||||
|
||||
def CreateCCFFChainPaths(dut):
|
||||
BitstreamXML = minidom.parse(
|
||||
glob.glob("./TESTBENCH/top/fabric_indepenent_bitstream.xml")[0])
|
||||
|
||||
ModulesDict = {}
|
||||
BT_BLocks = BitstreamXML.getElementsByTagName('bitstream_block')
|
||||
for element in BT_BLocks:
|
||||
if element.getAttribute('hierarchy_level') == "1":
|
||||
ModulesDict[element.attributes['name'].value] = element
|
||||
|
||||
FabricKey = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = FabricKey.getElementsByTagName('key')
|
||||
|
||||
pathList = OrderedDict()
|
||||
chainLength = 0
|
||||
|
||||
for elem in items:
|
||||
modulePaths = []
|
||||
moduleLen = 0
|
||||
inst = elem.attributes['alias'].value
|
||||
returnPaths(ModulesDict[inst], modulePaths)
|
||||
for eachEle in modulePaths:
|
||||
eachEle["obj"] = eval(eachEle["name"])
|
||||
moduleLen += eachEle["width"]
|
||||
pathList[inst] = modulePaths
|
||||
chainLength += moduleLen
|
||||
return (chainLength, pathList)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
CC = CreateCCFFChainPaths(None)
|
||||
pprint(CC["grid_clb_1__2_"][:5])
|
||||
pprint(len(CC["grid_clb_1__2_"]))
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
export PROJ_NAME=FPGA1212_SOFA_CHD # Project Name
|
||||
export FPGA_SIZE_X=12 # Grid X Size
|
||||
export FPGA_SIZE_Y=12 # Grid Y Size
|
||||
# Design Style [hier/flat], mostly hier
|
||||
export DESIGN_STYLE=hier
|
||||
export TECHNOLOGY="skywater"
|
||||
|
||||
# Complete Chip (fpga_top) or eFPGA (fpga_core)
|
||||
export DESIGN_NAME=fpga_core
|
||||
|
||||
# Pin Information Source Automatic or Sheet
|
||||
export PIN_MAP=Automatic
|
||||
export PIN_MAP_CSV_SPREADSHEET_LINK="" # Required only if PIN_MAP==Sheet
|
||||
|
||||
# Core Dimension, requires if DESIGN_NAME=fpga_core
|
||||
# if DESIGN_NAME=fpga_top its Optional if defined it overrides the
|
||||
# Calculated DIE_DIMENSION
|
||||
export DIE_DIMENSION=3200
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Derived Or Fixed Variables
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export OPENFPGA_ENGINE_PATH=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip
|
||||
export TASK_DIR_NAME=${PROJ_NAME}_task
|
||||
export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog
|
||||
export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt
|
||||
export POST_OPENFPGA_SCRIPT=./PostOpenFPGAScript.sh
|
||||
export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py
|
||||
export POST_GENERATION_SCRIPT=./generate_scandef_and_case_analysis.sh
|
||||
export MODULE_ADJUST=./adjust_module.sh
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Restructure Netlist Varaibles
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# export RESTRUCTURE_skipClockRestructure=""
|
||||
# export RESTRUCTURE_Skeleton=""
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# PNR RELATED FLOW
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export INIT_DESIGN_INPUT="ASCII"
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Extra variables availble during flow (suuffix FLOWVAR_)
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export FLOWVAR_STANDARD_CELLS="sc_hd"
|
||||
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Reference in New Issue